Machine instructions and addressing modes MCQs For Gate

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Machine Instructions and Addressing Modes (Computer Organization & Architecture)

Each question has options A–D, the correct answer, and a detailed solution.

  1. An ISA has a 16-bit instruction format. The opcode field is 5 bits and there are two register specifiers each 4 bits. How many bits remain for an immediate operand if the instruction uses immediate addressing?
    A. 2
    B. 3
    C. 7
    D. 8
    Answer: C
    Solution: Total 16 bits. Opcode 5 + 2×4 = 8 for registers → 5+8 =13. Remaining = 16−13 = 3 bits. Wait — but that gives 3. Recompute: Opcode 5, two regs 4+4=8 → 5+8=13 → 16−13=3. So correct is B (3). (Corrected)
    Final Answer: B
  1. A 32-bit machine uses byte addressing. An instruction is 4 bytes aligned. If PC = 0x1000 and a PC-relative branch has a signed 16-bit offset field that counts words (4-byte words), what is the branch target when the offset field equals −3?
    A. 0x0FF4
    B. 0x0FF0
    C. 0x0FEC
    D. 0x0FFC
    Answer: B
    Solution: Offset −3 in words ×4 = −12 bytes. Branch target = PC + offset_bytes = 0x1000 − 12 = 0x0FF4. But careful: some architectures add 4 before adding offset (delay slot). Problem states PC is 0x1000 and instruction is 4-byte aligned; assume PC points to next instruction. Standard: target = 0x1000 + (−3×4) = 0x1000 −12 = 0x0FF4. So A (0x0FF4). Final Answer: A
  1. Which addressing mode computes effective address as EA = base_register + sign-extended 12-bit immediate?
    A. Indexed addressing
    B. Base-displacement addressing
    C. Register indirect
    D. PC-relative
    Answer: B
    Solution: Base-displacement combines base register and displacement (immediate). Indexed often uses index register; PC-relative uses PC. So base-displacement is correct.
  1. Consider an instruction set where a load instruction uses addressing: MEM[ Rb + (Ri << 2) + disp ]. What common addressing capability does this implement?
    A. Base + index with scale and displacement
    B. Register indirect only
    C. PC-relative addressing
    D. Immediate addressing
    Answer: A
    Solution: Expression is base (Rb) + index (Ri) shifted (scale) + displacement (disp) — classic base+index+scale+disp addressing.
  1. A machine has 8 general registers (R0–R7). An instruction encoding uses 6 bits for opcode, 3 bits for destination register, and 3 bits for one source register. If the format is fixed 16 bits, how many bits remain for a second source or immediate?
    A. 4
    B. 6
    C. 3
    D. 0
    Answer: A
    Solution: 16 − (6+3+3) = 4 bits remain.
  1. Which addressing mode is best when implementing variable-length arrays with element size 4 bytes and index in register Ri?
    A. Immediate addressing
    B. Register indirect
    C. Scaled indexed addressing (base + index×4)
    D. Direct addressing
    Answer: C
    Solution: Scaled index (index×element_size) maps array index to byte offset efficiently.
  1. A load instruction uses direct addressing and includes a 20-bit absolute address field. What is the maximum memory it can address?
    A. 1 MB
    B. 4 MB
    C. 1,048,576 words
    D. 1,048,576 bytes
    Answer: D
    Solution: 20-bit address → 2^20 bytes = 1,048,576 bytes (1 MiB). So D.
  1. Which instruction class usually makes CISC machines require microcode?
    A. Fixed 32-bit RISC ALU operations
    B. Complex memory-to-memory string operations
    C. Simple register-to-register moves
    D. Immediate arithmetic with 8-bit immediates
    Answer: B
    Solution: Complex micro-operations (string copy, repeat instructions) are implemented via microcode.
  1. Given an addressing mode: Autoincrement (Ri)+ returns operand then Ri = Ri + 4. What typical data structure is this mode especially convenient for?
    A. Linked lists (pointers)
    B. Stack push (predecrement)
    C. Iterating elements of an array (word elements)
    D. Random memory access
    Answer: C
    Solution: Autoincrement by element size is great for scanning arrays.
  1. Which of the following is not a memory addressing mode?
    A. Register direct
    B. Immediate
    C. Displacement
    D. Register indirect
    Answer: B
    Solution: Immediate is operand encoded in instruction, not an address in memory.
  1. A 24-bit instruction format uses opcode 6 bits, reg spec 5 bits, mode specifier 3 bits, leaving 10 bits for address/immediate. If using two’s complement immediates, what is the signed immediate range?
    A. −512 to 511
    B. −256 to 255
    C. −1024 to 1023
    D. 0 to 1023
    Answer: A
    Solution: 10-bit signed two’s complement range = −2^9 to 2^9−1 = −512 to 511.
  1. In register indirect addressing (e.g., LOAD R1, (R2)), what does (R2) mean?
    A. Use R2 as immediate value
    B. Use memory at address contained in R2
    C. Use register R2 directly as the operand
    D. Use R2’s low byte only
    Answer: B
    Solution: Parentheses denote contents at memory address held in R2.
  1. Which addressing mode uses the program counter as the base to allow position-independent code?
    A. Immediate addressing
    B. PC-relative addressing
    C. Register direct
    D. Direct addressing
    Answer: B
    Solution: PC-relative uses PC and allows code relocation.
  1. A machine uses a 12-bit offset in base+offset addressing; offsets are unsigned. Base register contains 0x10000. If offset field is 0xFFF, what is the effective address?
    A. 0x10FFF
    B. 0x1FFFF
    C. 0x10FFC
    D. 0x20FFF
    Answer: A
    Solution: 0x10000 + 0x0FFF = 0x10FFF.
  1. Which addressing mode reduces instruction size for small offsets but complicates addressing of large data structures?
    A. Direct absolute addressing
    B. PC-relative with small signed offset
    C. Register indirect
    D. Base + large displacement
    Answer: B
    Solution: Small PC-relative offset encodes small ranges compactly but limits reach.
  1. An instruction format has 1-bit addressing mode flag: 0 → register direct (3-bit reg), 1 → memory direct (12-bit addr). Which instruction set design property is this demonstrating?
    A. Variable-length operands via mode bit
    B. Fixed register count
    C. Endianness selection
    D. Microprogramming
    Answer: A
    Solution: Mode bit selects operand interpretation; allows variant operand encodings.
  1. A system uses Big-Endian memory. A 32-bit value 0x12345678 is stored at address 0x2000. What byte is at address 0x2002?
    A. 0x12
    B. 0x34
    C. 0x56
    D. 0x78
    Answer: C
    Solution: Big-endian stores bytes as 12 34 56 78 at addresses 2000..2003. addr 2002 => 0x56.
  1. Which addressing mode is usually used for passing parameters in a stack machine?
    A. Immediate
    B. Register direct
    C. Stack relative (using SP + offset)
    D. PC-relative
    Answer: C
    Solution: Stack relative addresses parameters on stack via SP offsets.
  1. A 16-bit instruction set uses one addressing bit that toggles between short and long immediate forms. If short takes 5 bits and long consumes remaining 11 bits, what tradeoff is being used?
    A. Code density vs immediate range
    B. Separate data and instruction spaces
    C. Little vs big endian
    D. Microcoding vs hardwired control
    Answer: A
    Solution: Short immediate saves bits for compact code; long immediate sacrifices density for range.
  1. Which addressing mode can implement both call and jump tables efficiently?
    A. Register direct
    B. Indexed indirect (e.g., load address from table + indirect)
    C. Immediate only
    D. Stack only
    Answer: B
    Solution: Indexed to table base + indirect fetch lets dynamic dispatch via table entries.
  1. Consider a displacement addressing mode where displacement is signed 8 bits. On a 64-bit machine, the effective address is base + sign_extension(disp). If base = 0x7FFF_FFFF_FFFF_F000 and disp = 0x80 (−128), what is EA?
    A. 0x7FFF_FFFF_FFFF_F080
    B. 0x7FFF_FFFF_FFFF_F000 − 128 = 0x7FFF_FFFF_FFFF_FE80
    C. 0x8000_0000_0000_0000
    D. 0x7FFF_FFFF_FFFF_F0FF
    Answer: B
    Solution: Sign-extended 0x80 = −128. EA = base − 128 = 0x7FFF…F000 − 0x80 = 0x7FFF…FE80.
  1. Which addressing mode is most compact for frequently used constants?
    A. Memory indirect
    B. Immediate addressing
    C. Register indirect
    D. PC-relative
    Answer: B
    Solution: Immediate encodes constant directly in instruction.
  1. A machine supports indexed addressing: EA = base + index. If base = 0x4000, index register contains 0xFFFC (−4 signed 16-bit), what EA is produced assuming index is sign-extended?
    A. 0x3FFC
    B. 0x4FFC
    C. 0x4004
    D. 0x3FFD
    Answer: A
    Solution: Index −4 → EA = 0x4000 − 4 = 0x3FFC.
  1. In an instruction using autodecrement addressing (−(R1)), what typical use is it associated with?
    A. Array forward scan
    B. Stack push (predecrement before store)
    C. Random access table lookup
    D. PC-relative branch
    Answer: B
    Solution: Predecrement used for pushing onto stack (stack grows downward).
  1. A 3-address instruction encoding: OPCODE (6) | Rd (5) | Rs (5) | Rt (5) — total 21 bits. If instruction word must be 32 bits, how many bits left for other uses?
    A. 8
    B. 11
    C. 16
    D. 5
    Answer: B
    Solution: 32 − 21 = 11 bits remaining.
  1. Which addressing mode requires an extra memory access to fetch the actual operand address?
    A. Direct addressing
    B. Register direct
    C. Indirect addressing (memory indirect)
    D. Immediate addressing
    Answer: C
    Solution: Indirect: first fetch pointer from memory, then fetch operand — two memory accesses.
  1. Given a 64-KB (2^16 bytes) memory and 16-bit absolute addressing encoded in the instruction, what addressing mode is being used?
    A. PC-relative
    B. Direct absolute addressing
    C. Indexed
    D. Register indirect
    Answer: B
    Solution: 16-bit absolute address field gives direct absolute addressing over 64KB.
  1. Which addressing mode is commonly used for efficient switch/case implementations using a jump table?
    A. Immediate
    B. PC-relative indexed addressing (PC + offset + index×entry_size)
    C. Register direct
    D. Memory indirect only
    Answer: B
    Solution: Jump table uses PC-relative base + index offset.
  1. A machine supports sign extension of immediate fields. Which instruction semantics are affected by sign extension?
    A. Logical shift right
    B. Arithmetic operations that use immediate operands (e.g., addi)
    C. Register move only
    D. Floating point add
    Answer: B
    Solution: Arithmetic immediates must be sign-extended for correct negative values.
  1. A load uses direct addressing with a 10-bit offset and base 0x8000. If offset is 0b11_1111_1111 (decimal 1023), EA = ?
    A. 0x83FF
    B. 0x8FFF
    C. 0x8003FF
    D. 0x83F0
    Answer: A
    Solution: 0x8000 + 1023 = 0x8000 + 0x03FF = 0x83FF.
  1. Which addressing mode is most likely used to implement function return addresses?
    A. PC-relative registers
    B. Register indirect
    C. Stack relative (push return address onto stack)
    D. Immediate
    Answer: C
    Solution: Call pushes return address on stack or stores in link register; stack relative is common.
  1. An ISA provides both 8-bit and 32-bit immediate forms. Compiler selects 8-bit when possible to improve code density. This is an example of which design tradeoff?
    A. Hardware simplicity vs microcode
    B. Code density vs expressiveness (immediate range)
    C. Endianness vs alignment
    D. Pipelining vs superscalar
    Answer: B
    Solution: Smaller immediate → better density but smaller range.
  1. If a memory operand is specified by (Rbp + disp) where disp is 16 bits signed, and Rbp = 0x7FFF_FFFF_FFF0_0000, disp = 0x8000 (−32768), EA = ?
    A. 0x7FFF_FFFF_FFE7_8000
    B. 0x7FFF_FFFF_FFF0_0000 − 32768 = 0x7FFF_FFFF_FFE7_8000
    C. 0x7FFF_FFFF_FFF0_0000 + 32768
    D. Undefined
    Answer: B
    Solution: Signed disp −32768; subtract from base: base − 0x8000 = 0x…E7_8000.
  1. Which addressing mode requires the least CPU cycles for accessing small local variables in register-rich architectures?
    A. Direct memory addressing
    B. Register direct addressing
    C. Indirect through memory
    D. PC-relative
    Answer: B
    Solution: Register access is fastest.
  1. For an architecture with byte-addressable memory and 4-byte words, which addressing mode must scale an index by 4 when index holds element number?
    A. Immediate
    B. Scaled indexed addressing
    C. Register direct
    D. PC-relative
    Answer: B
    Solution: Scaled index multiplies index by element size.
  1. A 2-operand architecture encodes: OPCODE (6) | Reg/mode (5) | Operand (11). Operand field may be register (5) or 11-bit immediate. If mode bit indicates register vs immediate, what advantage is offered?
    A. Supports both register and immediate operands compactly
    B. Eliminates need for opcode
    C. Ensures fixed instruction length of 16 bits
    D. Enables microprogramming
    Answer: A
    Solution: Mode bit allows operand field to be interpreted variably — flexible compact encoding.
  1. Which addressing mode can create data hazards in pipelined processors when using autoincrement or autodecrement?
    A. Immediate addressing
    B. Autoincrement / autodecrement (post/pre) addressing
    C. Register direct without side effects
    D. Direct addressing
    Answer: B
    Solution: Side effect on register makes hazard detection and forwarding more complex.
  1. A machine with 32-bit instructions supports an instruction: LOAD Ri, [disp8] where disp8 is unsigned and base is implicit 0x40000000. If disp8 = 200, EA is: (in hex)
    A. 0x400000C8
    B. 0x40000064
    C. 0x4000C800
    D. 0x40000000
    Answer: A
    Solution: 200 dec = 0xC8. EA = 0x40000000 + 0xC8 = 0x400000C8.
  1. Which addressing mode is preferred for compact code in embedded systems with many small constants?
    A. Large 32-bit absolute addressing
    B. Short immediates (8 or 12 bit) embedded in instructions
    C. Indirect addressing via memory pointers
    D. PC-relative only
    Answer: B
    Solution: Small immediates increase code density for frequent small constants.
  1. A machine implements load/store with 12-bit signed displacement from base register. What is the signed byte range a displacement can address?
    A. −2048 to 2047 bytes
    B. −4096 to 4095 bytes
    C. 0 to 4095 bytes
    D. −1024 to 1023 bytes
    Answer: A
    Solution: 12-bit signed two’s complement: −2^(11) to 2^(11)−1 = −2048 to 2047.
  1. An instruction set supports autoindexing: LOAD R1, (R2)+ where R2 increments by 8. Which data type size is this most natural for?
    A. 1-byte char arrays
    B. 2-byte short arrays
    C. 4-byte int arrays
    D. 8-byte double arrays
    Answer: D
    Solution: Increment by 8 implies element size 8 bytes → doubles or 64-bit words.
  1. Which addressing mode helps implement position-independent code (PIC) for shared libraries?
    A. Absolute addressing with fixed addresses
    B. PC-relative addressing and GOT/PLT based indirect referencing
    C. Immediate addressing only
    D. Register direct rigid mapping
    Answer: B
    Solution: PIC uses PC-relative addressing and global offset table (GOT) indirection.
  1. Given a 16-bit instruction where the last 8 bits are immediate and interpreted unsigned, what’s the largest immediate value represented?
    A. 255
    B. 127
    C. 1023
    D. 65535
    Answer: A
    Solution: 8-bit unsigned max = 2^8 −1 = 255.
  1. A branch instruction uses 8-bit signed offset in words on a 64-bit machine with 8-byte words. Maximum forward branch distance in bytes is:
    A. 2040
    B. 1024
    C. 2048
    D. 1016
    Answer: A
    Solution: 8-bit signed range = −128..127 words. Max forward = 127 words × 8 bytes = 1016 bytes. Wait compute: 127×8 = 1016. So D (1016). Final Answer: D
  1. Which addressing mode can most naturally implement object field access in OO languages when object base is in a register and field offset known at compile time?
    A. Register indirect
    B. Base+displacement (object_base + field_offset)
    C. PC-relative
    D. Immediate only
    Answer: B
    Solution: Field offset added to object base register yields EA directly.
  1. CPU uses little-endian and 32-bit words. Memory at 0x3000..0x3003 = 0xAA 0xBB 0xCC 0xDD. Interpreting as 32-bit little-endian value gives:
    A. 0xAABBCCDD
    B. 0xDDCCBBAA
    C. 0xBBCCDDAA
    D. 0xDDCCBBAA (same as B)
    Answer: B
    Solution: Little-endian: lowest address holds least significant byte: value = 0xDDCCBBAA. So B.
  1. Which addressing mode is used when instruction contains an address stitched into instruction bytes (common in older CISC)?
    A. Immediate
    B. Absolute direct addressing (absolute operand address in instruction)
    C. Register indirect
    D. PC-relative
    Answer: B
    Solution: Absolute direct has the full address in instruction.
  1. A 3-byte instruction: opcode (8) + reg1 (4) + reg2 (4) + mode (4) = 20 bits, with remaining 4 bits unused — what design waste does this illustrate?
    A. Bit field fragmentation due to fixed instruction sizes and odd field widths
    B. Endianness mismatch
    C. Microcoding overhead
    D. None
    Answer: A
    Solution: Unused bits are due to fragmentation and alignment of fields in fixed-size instruction words.
  1. Which addressing mode can be accelerated via a dedicated address generation unit (AGU) in pipelines?
    A. Immediate addressing (no AGU needed)
    B. Complex base+index+scale+disp addressing
    C. Register direct only
    D. None
    Answer: B
    Solution: AGUs compute complex EA (base + index*scale + displacement) quickly.
  1. In a load/store pipeline, which addressing mode increases risk of multiple memory accesses per instruction?
    A. Register direct
    B. Indirect memory addressing (memory-indirect)
    C. Immediate addressing
    D. Register indirect without additional memory reads
    Answer: B
    Solution: Memory-indirect first reads pointer from memory, then reads target → two memory accesses, increasing pipeline pressure.

Perfect 👍 Let’s continue — here are the remaining 51–100 advanced and plagiarism-free MCQs on Machine Instructions & Addressing Modes for GATE (Computer Organization & Architecture) with full solutions and varied numerical setups.

⚙️ Machine Instructions & Addressing Modes (51–100)

51.

In a 32-bit architecture, an instruction format has 8-bit opcode, two 4-bit register specifiers, and a 16-bit immediate field. How many distinct opcodes are possible?
A. 16
B. 64
C. 128
D. 256
Answer: D
Solution: Opcode field = 8 bits ⇒ (2^8 = 256) distinct opcodes.

52.

An instruction uses PC-relative addressing with an 8-bit signed offset (in bytes). If PC = 0x4000 and offset = 0xF0, what is the branch target?
A. 0x3FF0
B. 0x4010
C. 0x3FF0 (−16 bytes)
D. 0x3F10
Answer: C
Solution: Offset = 0xF0 = −16 (two’s complement). Target = 0x4000 − 16 = 0x3FF0.

53.

In a load instruction LOAD R1, (R2)+, which step happens first?
A. R2 incremented
B. Memory accessed
C. R1 incremented
D. PC modified
Answer: B
Solution: Autoincrement → fetch memory at (R2), then increment R2.

54.

A 24-bit instruction format uses: opcode 6 bits, mode 2 bits, register 4 bits, and address field for the rest. What is the address field size?
A. 10 bits
B. 12 bits
C. 24 bits
D. 20 bits
Answer: B
Solution: Remaining = 24 − (6+2+4) = 12 bits.

55.

Which addressing mode allows implementing loops with constant step size easily without modifying the instruction itself?
A. Immediate
B. Indexed (Base + Index × Scale)
C. Direct
D. Register indirect
Answer: B
Solution: Indexed allows automatic increment via index register for looping.

56.

A system uses 32-bit instructions. For a 3-address instruction with 8-bit opcode and 3×6-bit registers, how many bits are unused?
A. 2
B. 6
C. 32 − (8 + 18) = 6 bits
D. 0
Answer: C
Solution: 8+18=26 bits used, 32−26=6 bits free.

57.

Which addressing mode uses a pointer fetched from memory to locate the actual operand?
A. Memory indirect
B. Indexed
C. Immediate
D. Base-displacement
Answer: A
Solution: Memory indirect means one memory fetch for pointer, second for data.

58.

In register indirect mode, if R2 = 0x8000 and memory[0x8000] = 0xAB, executing LOAD R1, (R2) results in R1 = ?
A. 0x8000
B. 0xAB
C. 0x00
D. 0xFFFF
Answer: B
Solution: Loads data from memory address contained in R2.

59.

Which instruction form typically needs more instruction fetch bandwidth?
A. Fixed-length RISC instructions
B. Variable-length CISC instructions
C. Immediate-only instructions
D. Register direct instructions
Answer: B
Solution: Variable length increases fetch bandwidth due to unpredictability.

60.

What is the main advantage of using displacement (base + offset) addressing over absolute addressing?
A. Larger addressing range
B. Enables relocatable and modular code
C. Simpler decoding
D. No need for registers
Answer: B
Solution: Base-displacement supports relocatable code—offsets adjusted easily.

61.

A 32-bit address space requires how many bits of displacement for 4KB page offset?
A. 10
B. 12
C. 16
D. 8
Answer: B
Solution: 4KB = 2¹² → 12 bits for page offset.

62.

Which addressing mode helps efficiently implement stack-based arithmetic expression evaluation?
A. Register direct
B. Immediate
C. Stack addressing (implicit top-of-stack)
D. Indexed
Answer: C
Solution: Stack addressing eliminates explicit operand fields.

63.

A register holds base = 0x2000, offset = 0x0030. In base + offset addressing, EA = ?
A. 0x2030
B. 0x2020
C. 0x2003
D. 0x3000
Answer: A
Solution: EA = base + offset = 0x2000 + 0x30 = 0x2030.

64.

Which addressing mode results in the largest instruction size for the same architecture?
A. Register direct
B. Immediate (large constant)
C. Indexed
D. Autoincrement
Answer: B
Solution: Immediate constants take more bits, enlarging instruction.

65.

A processor supports 16 general-purpose registers. Minimum bits to specify a register?
A. 3
B. 4
C. 5
D. 2
Answer: B
Solution: 2⁴ = 16 → 4 bits required.

66.

In displacement mode, if base = R3 = 0x1000, displacement = −8 (signed), EA = ?
A. 0x0FF8
B. 0x1008
C. 0x1FF8
D. 0x0F00
Answer: A
Solution: EA = 0x1000 − 8 = 0x0FF8.

67.

Which of the following is an example of a zero-address instruction format?
A. ADD R1, R2, R3
B. ADD R1, R2
C. ADD
D. ADD (R1), (R2)
Answer: C
Solution: Zero-address implies stack architecture; operands on top of stack.

68.

A CPU supports 2-address instructions. Which operation is invalid in this format?
A. MOV R1, R2
B. ADD R1, R2
C. MUL R1, R2
D. ADD R1, R2, R3
Answer: D
Solution: 2-address allows at most two operands—destination overwrites one.

69.

Which addressing mode enables compact encoding for jump distances within ±2KB?
A. Direct absolute
B. PC-relative 12-bit signed offset
C. Indexed
D. Register indirect
Answer: B
Solution: ±2KB = ±2048 bytes → 12-bit signed offset.

70.

Which addressing mode directly supports array element access given base address and index in register?
A. Indexed
B. Immediate
C. Indirect
D. Direct
Answer: A
Solution: Indexed = base + index × element size.

71.

In instruction MOV A, (B), what does (B) represent?
A. Address of memory location stored in B
B. Immediate constant
C. Label address
D. Register pair
Answer: A
Solution: Parentheses denote indirect reference to memory via register B.

72.

A processor supports auto-increment addressing. What hazard can occur in pipelines?
A. Control hazard
B. Structural hazard
C. Data hazard due to register modification
D. None
Answer: C
Solution: Register is modified and reused before increment completes.

73.

Which addressing mode allows code to execute correctly even if relocated in memory?
A. PC-relative
B. Absolute
C. Direct
D. Immediate
Answer: A
Solution: PC-relative uses offset independent of absolute memory location.

74.

A memory operand is located using: EA = (R1) + (R2) + disp. Which is true?
A. Double indirect mode
B. Indexed base-displacement mode
C. Immediate mode
D. None
Answer: B
Solution: Combines base register, index register, and displacement.

75.

What is the key difference between direct and immediate addressing?
A. Immediate uses operand value; direct uses operand address.
B. Immediate uses memory location; direct uses register.
C. Both use memory operands.
D. Immediate slower than direct.
Answer: A
Solution: Direct = memory address; immediate = value embedded in instruction.

76.

In an instruction format, operand specifier = 6 bits. If 2 bits define addressing mode, how many registers can be encoded?
A. 16
B. 8
C. 4
D. 12
Answer: B
Solution: Remaining bits = 6−2=4 bits ⇒ 2⁴=16 possible registers.

77.

A CPU instruction: MOV (R1)+, R2. What operation occurs?
A. Load from R1, then increment R1, store into R2
B. Store R2 into R1
C. Increment R2
D. Swap contents
Answer: A
Solution: Autoincrement fetch then increments pointer.

78.

Which addressing mode is best for implementing pointer-linked data structures (like linked lists)?
A. Immediate
B. Indirect
C. Indexed
D. Displacement
Answer: B
Solution: Indirect addressing allows traversing pointer fields.

79.

What is the main advantage of register indirect addressing?
A. No need for registers
B. Enables dynamic data structure access
C. Simplifies decoding
D. Uses less memory
Answer: B
Solution: Address held in register can be changed dynamically—pointers, stacks.

80.

A 20-bit address bus allows maximum addressing range of:
A. 1 MB
B. 2 MB
C. 512 KB
D. 4 MB
Answer: A
Solution: (2^{20}) bytes = 1 MB.

81.

Which addressing mode computes EA = (Base Register + (Index × Scale) + Displacement)?
A. Complex effective address (Intel x86 style)
B. Direct
C. Immediate
D. Register indirect
Answer: A
Solution: Used in x86: base+index*scale+disp.

82.

Which addressing mode reduces instruction fetches for frequently used constants?
A. Immediate
B. Register indirect
C. Indexed
D. PC-relative
Answer: A
Solution: Immediate embeds constant directly.

83.

A 2-byte instruction has 4-bit opcode and two 4-bit register specifiers. How many bits remain?
A. 8
B. 4
C. 0
D. 12
Answer: B
Solution: 16 − (4+4+4) = 4 bits left.

84.

Which addressing mode helps implement relative branch for control flow?
A. PC-relative
B. Direct
C. Indirect
D. Immediate
Answer: A
Solution: PC-relative offset adjusts target relative to current instruction.

85.

Which addressing mode is most suitable for reading consecutive bytes from a buffer in memory?
A. Autoincrement
B. Register direct
C. Immediate
D. Indexed
Answer: A
Solution: Auto-increment increments pointer automatically after access.

86.

An instruction fetches operand from memory and updates address register by decrementing it. Which mode is it?
A. Autoincrement
B. Autodecrement
C. Indirect
D. Indexed
Answer: B
Solution: Decrement register → predecrement mode.

87.

A 32-bit instruction has an immediate field of 12 bits. If immediate is signed, what’s its range?
A. −4096 to +4095
B. −2048 to +2047
C. 0 to 4095
D. −512 to +511
Answer: B
Solution: 12-bit signed ⇒ −2¹¹ … 2¹¹−1 = −2048 to 2047.

88.

Which addressing mode is most common in implementing jump instructions?
A. PC-relative
B. Immediate
C. Indexed
D. Stack
Answer: A
Solution: PC-relative for short-range branch/jump.

89.

What is the major limitation of immediate addressing?
A. Operand cannot be modified at runtime
B. Large memory usage
C. Slower execution
D. Needs extra cycle
Answer: A
Solution: Immediate operand fixed in instruction → read-only constant.

90.

Instruction: LOAD R3, #45H uses which addressing mode?
A. Direct
B. Immediate
C. Indirect
D. PC-relative
Answer: B
Solution: # denotes immediate operand (constant 0x45).

91.

Instruction: MOV R1, 5000H loads content from address 5000H. Addressing mode?
A. Immediate
B. Direct
C. Indirect
D. Register direct
Answer: B
Solution: Address embedded → direct addressing.

92.

Instruction: MOV R1, @R2 loads from memory whose address stored in R2. Addressing mode?
A. Register indirect
B. Direct
C. Indexed
D. PC-relative
Answer: A
Solution: @ or () denotes indirect.

93.

Which addressing mode allows referencing memory locations near current instruction efficiently?
A. PC-relative
B. Indexed
C. Immediate
D. Direct
Answer: A
Solution: PC-relative addresses nearby code/data.

94.

If 10 bits are used for opcode in 32-bit instruction, how many unique instructions can the machine support?
A. 512
B. 1024
C. 256
D. 2048
Answer: B
Solution: (2^{10} = 1024) instructions.

95.

Which addressing mode is ideal for implementing recursion?
A. Stack-relative
B. Immediate
C. Direct
D. PC-relative
Answer: A
Solution: Stack-relative enables dynamic activation records.

96.

For a 16-bit instruction with 5-bit opcode, 3-bit register, and 8-bit immediate, what is the immediate range (unsigned)?
A. 0–255
B. −128–127
C. 0–127
D. 0–1023
Answer: A
Solution: 8-bit unsigned ⇒ 0–255.

97.

Instruction JMP (R3) performs jump to address in R3. Addressing mode?
A. Register indirect
B. Direct
C. Immediate
D. Indexed
Answer: A
Solution: Jump via register ⇒ register indirect.

98.

Which addressing mode saves instruction bits when most operands are stored in registers?
A. Register direct
B. Indexed
C. Immediate
D. Direct
Answer: A
Solution: Register fields smaller than memory addresses ⇒ compact.

99.

Which addressing mode allows an instruction to reference data from different segments like DS, CS in x86 architecture?
A. Segment-based addressing (Base + Segment + Offset)
B. Immediate
C. Indexed
D. Stack
Answer: A
Solution: x86 uses segment registers to form linear address.

100.

Which addressing mode is used when the operand itself is part of the instruction, requiring no memory fetch?
A. Immediate
B. Direct
C. Indirect
D. Indexed
Answer: A
Solution: Operand embedded directly → immediate addressing.