I/O Interface, Interrupts, and DMA Mode MCQs in C Language
I/O Interface, Interrupts, and DMA Mode MCQs
1
In programmed I/O, the CPU waits until the I/O operation is complete. This type of I/O is also called:
A. Polling
B. Interrupt-driven
C. DMA
D. Buffered I/O
Answer: A
Solution:
Programmed I/O requires CPU to continuously check I/O status โ called polling.
2
CPU cycles wasted in programmed I/O are reduced by:
A. Interrupts
B. Direct memory access
C. Faster CPU
D. Larger cache
Answer: A
Solution:
Interrupts allow CPU to perform other tasks and respond to I/O only when device signals completion.
3
In interrupt-driven I/O, the CPU executes other instructions until:
A. Device interrupts
B. Memory is full
C. Program ends
D. DMA completes
Answer: A
Solution:
Interrupt signals CPU that I/O is ready โ CPU responds only then.
4
Interrupt vector contains:
A. Address of interrupt service routine
B. CPU register contents
C. Memory size
D. Stack pointer
Answer: A
Solution:
Interrupt vector points to service routine to handle the interrupt.
5
A CPU with multiple devices needs:
A. Prioritized interrupts
B. Single-level cache
C. DMA
D. Programmed I/O only
Answer: A
Solution:
Prioritization ensures critical devices are served first.
6
DMA (Direct Memory Access) allows:
A. I/O device to transfer data directly to memory
B. CPU to do all I/O operations
C. Only input to CPU
D. Only output from CPU
Answer: A
Solution:
DMA controller transfers data between memory and I/O without CPU intervention โ reduces CPU overhead.
7
In DMA, CPU is halted for:
A. Brief bus cycle (cycle stealing)
B. Entire I/O operation
C. DMA never halts CPU
D. Only read operations
Answer: A
Solution:
Cycle stealing allows DMA to temporarily use the bus โ CPU continues other instructions with minor delay.
8
In memory-mapped I/O, device registers share:
A. Address space with memory
B. Separate I/O port space
C. Cache lines
D. DMA channels
Answer: A
Solution:
Memory-mapped I/O uses same address space for memory and I/O devices.
9
Isolated I/O uses:
A. Separate address space for I/O devices
B. Memory address space
C. Cache memory
D. DMA only
Answer: A
Solution:
I/O devices have distinct addresses โ CPU uses specific IN/OUT instructions.
10
Interrupt-driven I/O is preferred over programmed I/O because:
A. Reduces CPU waiting
B. Increases CPU wait
C. Reduces I/O speed
D. Requires more memory
Answer: A โ
11
A vectored interrupt provides:
A. Direct address of ISR
B. CPU status
C. Memory size
D. DMA status
Answer: A
Solution:
CPU knows exact location of service routine โ faster response.
12
Non-vectored interrupt requires:
A. CPU to poll interrupting device
B. Device to provide address
C. DMA
D. Cache
Answer: A
Solution:
CPU determines source โ slower than vectored interrupt.
13
In priority interrupt, device with highest priority:
A. Serviced first
B. Serviced last
C. Random order
D. Disabled
Answer: A โ
14
Interrupt latency is:
A. Time from interrupt request to ISR execution
B. Total I/O time
C. CPU cycle time
D. DMA transfer time
Answer: A โ
15
Which register saves CPU state during interrupt?
A. Program Counter (PC)
B. Memory Address Register
C. Accumulator
D. Instruction Register
Answer: A
Solution:
PC saved on stack โ ISR execution โ restore PC afterward.
16
DMA transfers block of 1024 bytes, bus width = 16 bits. Number of transfers = ?
A. 512
B. 1024
C. 2048
D. 256
Answer: A
Solution:
16-bit bus = 2 bytes per transfer
Number of transfers = 1024 /2 = 512 transfers
17
In cycle stealing DMA, CPU:
A. Temporarily relinquishes bus
B. Halted until I/O complete
C. Ignored
D. Disabled
Answer: A โ
18
In burst mode DMA, CPU is:
A. Halted for full block transfer
B. Free for other tasks
C. Polling
D. Cache disabled
Answer: A โ
19
Interrupt priority can be implemented by:
A. Daisy-chaining
B. Separate cache
C. Direct memory access
D. Memory-mapped I/O
Answer: A โ
20
In polling, CPU checks device:
A. Repeatedly
B. Only once
C. Never
D. Through DMA
Answer: A โ
21
Which I/O mode reduces CPU overhead most?
A. DMA
B. Programmed I/O
C. Interrupt-driven I/O
D. Polling
Answer: A โ
22
Interrupt-driven I/O is slower than DMA because:
A. CPU handles each data word
B. DMA cannot transfer
C. CPU is halted entirely
D. Polling required
Answer: A โ
23
During DMA transfer, CPU performs:
A. Other operations except bus cycles
B. No operation
C. Only I/O
D. Instruction fetch halted
Answer: A โ
24
DMA controller needs:
A. Address, count, control signals
B. Cache info
C. Stack pointer
D. CPU registers only
Answer: A โ
25
Interrupt vector table stored at:
A. Fixed memory location
B. Stack
C. Cache
D. DMA buffer
Answer: A โ
26
Highest priority interrupt in daisy chain is:
A. First device in chain
B. Last device
C. Random device
D. CPU
Answer: A โ
27
DMA transfer block = 2 KB, bus width = 16 bits, CPU cycles per transfer = 1. Number of cycles CPU blocked in burst mode?
A. 1024
B. 2048
C. 512
D. 4096
Answer: A
Solution:
2 KB = 2048 bytes, bus=16 bits=2 bytes/transfer โ transfers=1024 โ CPU halted 1024 cycles in burst.
28
Interrupt vector table contains:
A. ISR addresses
B. Stack pointer
C. CPU frequency
D. DMA status
Answer: A โ
29
In vectored interrupt, CPU fetches ISR address:
A. Automatically from vector
B. Polls device
C. From memory only
D. From cache
Answer: A โ
30
Non-vectored interrupt โ CPU finds ISR by:
A. Polling devices
B. Reading vector table
C. DMA transfer
D. Cache
Answer: A โ
31
Device interrupts CPU โ ISR saves:
A. Registers, PC
B. Cache lines
C. DMA status
D. Memory contents
Answer: A โ
32
DMA transfers block 4096 bytes, bus width=32 bits โ transfers = ?
A. 1024
B. 2048
C. 4096
D. 512
Answer: A
Solution:
32-bit bus =4 bytes/transfer โ 4096 /4=1024 transfers
33
CPU halted for 1 bus cycle per transfer โ type of DMA?
A. Cycle stealing
B. Burst mode
C. Programmed I/O
D. Interrupt-driven
Answer: A โ
34
CPU halted for entire block transfer โ type of DMA?
A. Burst mode
B. Cycle stealing
C. Polling
D. Programmed I/O
Answer: A โ
35
During interrupt, CPU executes ISR โ stack used to:
A. Save return address and registers
B. Save DMA buffer
C. Save cache lines
D. Save memory
Answer: A โ
36
I/O mapped into memory โ addressing method?
A. Memory-mapped I/O
B. Isolated I/O
C. DMA
D. Interrupt
Answer: A โ
37
I/O mapped into separate address space โ ?
A. Isolated I/O
B. Memory-mapped I/O
C. DMA
D. Interrupt
Answer: A โ
38
I/O read โ CPU instruction?
A. IN/OUT (isolated I/O)
B. LOAD/STORE
C. FETCH/EXECUTE
D. DMA transfer
Answer: A โ
39
DMA reduces CPU involvement because:
A. Transfers data directly between memory & device
B. CPU executes each transfer
C. CPU polls devices
D. None
Answer: A โ
40
CPU polls I/O device continuously โ main disadvantage:
A. Wastes CPU cycles
B. Increases memory
C. Faster I/O
D. Reduces bus traffic
Answer: A โ
41
Interrupt vector table contains:
A. ISR addresses
B. Memory contents
C. Cache lines
D. DMA registers
Answer: A โ
42
Highest priority interrupt served first โ implemented by:
A. Daisy chain
B. Cache
C. Memory
D. DMA
Answer: A โ
43
DMA cycle stealing โ advantage:
A. CPU not halted for full block
B. Faster than burst mode
C. CPU always halted
D. None
Answer: A โ
44
DMA burst mode โ advantage:
A. High transfer rate
B. CPU free
C. Reduces bus width
D. Slower
Answer: A โ
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45
Interrupt service routine โ must restore:
A. CPU registers & PC
B. DMA status
C. Memory content
D. Cache
Answer: A โ
46
Interrupt latency depends on:
A. CPU speed, instruction cycles
B. DMA width
C. Cache only
D. Memory size
Answer: A โ
47
CPU priority interrupts โ implemented by:
A. Daisy chaining or polling
B. DMA
C. Cache
D. Stack
Answer: A โ
48
CPU receives interrupt while servicing another โ type?
A. Nested interrupt
B. Cycle stealing
C. Burst mode
D. Polling
Answer: A โ
49
CPU instruction to initiate DMA transfer โ store in:
A. DMA registers
B. Stack
C. Cache
D. Memory only
Answer: A โ
50
DMA controller needs which registers?
A. Source address, destination address, byte count, control
B. PC only
C. Cache lines
D. Stack pointer
Answer: A โ
51
DMA transfer block = 8 KB, bus width = 32 bits โ number of transfers?
A. 2048
B. 1024
C. 512
D. 4096
Answer: A
Solution:
Bus width = 32 bits = 4 bytes/transfer
Block size = 8 KB = 8192 bytes
Number of transfers = 8192 /4 = 2048 transfers
52
CPU halted only for bus cycles during DMA โ type of DMA?
A. Cycle stealing
B. Burst mode
C. Programmed I/O
D. Interrupt-driven I/O
Answer: A โ
53
CPU halted for entire DMA block โ type of DMA?
A. Burst mode
B. Cycle stealing
C. Polling
D. Programmed I/O
Answer: A โ
54
Number of interrupt levels determines:
A. Number of priority levels
B. Cache size
C. DMA transfer rate
D. Memory width
Answer: A โ
55
Daisy-chain interrupt โ disadvantage:
A. Lower priority device delayed
B. More memory required
C. Slower DMA
D. CPU halted
Answer: A โ
56
VECTORED INTERRUPT โ advantage over non-vectored?
A. Faster ISR fetch
B. CPU halted
C. DMA needed
D. Polling required
Answer: A โ
57
Non-vectored interrupt โ CPU finds ISR by:
A. Polling device
B. Vector table
C. DMA
D. Cache
Answer: A โ
58
Nested interrupts allowed if:
A. Higher priority interrupts allowed during ISR
B. CPU halted
C. Only DMA active
D. Polling active
Answer: A โ
59
Interrupt mask register used to:
A. Enable/disable specific interrupts
B. Store DMA data
C. Track memory
D. Cache lines
Answer: A โ
60
CPU executes which instruction to enable interrupts?
A. EI (Enable Interrupts)
B. DI
C. NOP
D. LOAD
Answer: A โ
61
CPU executes which instruction to disable interrupts?
A. DI (Disable Interrupts)
B. EI
C. NOP
D. STORE
Answer: A โ
62
Interrupt vector table located at:
A. Fixed memory location
B. Stack
C. DMA buffer
D. Cache
Answer: A โ
63
During DMA, CPU is free to execute instructions โ unless:
A. Cycle stealing
B. Burst mode
C. Programmed I/O
D. Polling
Answer: A โ
64
DMA controller register holds:
A. Source address, destination address, count
B. CPU flags
C. Stack pointer
D. Cache lines
Answer: A โ
65
DMA transfer complete โ CPU notified by:
A. Interrupt
B. Polling
C. Cache
D. Stack
Answer: A โ
66
DMA transfer reduces CPU involvement by:
A. Directly moving data memory โ device
B. CPU polling
C. CPU executes each I/O
D. None
Answer: A โ
67
In cycle stealing DMA, CPU executes:
A. Other instructions during DMA
B. No instructions
C. Only I/O
D. Polling
Answer: A โ
68
Interrupt latency formula:
A. Time from request โ ISR execution
B. CPU cycle only
C. DMA transfer time
D. Cache fetch
Answer: A โ
69
Number of DMA channels affects:
A. Number of simultaneous transfers
B. CPU clock
C. Cache lines
D. Stack size
Answer: A โ
70
Interrupt request serviced โ CPU state saved in:
A. Stack
B. Cache
C. DMA buffer
D. Memory
Answer: A โ
71
I/O mapped into memory โ addressing method?
A. Memory-mapped I/O
B. Isolated I/O
C. DMA only
D. Interrupt only
Answer: A โ
72
Separate address space for I/O โ method?
A. Isolated I/O
B. Memory-mapped I/O
C. DMA only
D. Interrupt only
Answer: A โ
73
Interrupt priority โ can be implemented by:
A. Daisy chain
B. Stack
C. Cache
D. Bus width
Answer: A โ
74
DMA transfer 1 KB, bus = 16-bit โ transfers = ?
A. 512
B. 1024
C. 256
D. 2048
Answer: A โ
Solution:
1 KB = 1024 bytes; bus = 16 bits = 2 bytes โ 1024 /2 = 512 transfers
75
DMA block = 4 KB, bus = 32 bits โ transfers?
A. 1024
B. 512
C. 2048
D. 4096
Answer: A โ
76
CPU halted during DMA block โ burst mode โ advantage?
A. Fast transfer
B. CPU free
C. Reduce bus width
D. Polling faster
Answer: A โ
77
Cycle stealing DMA โ disadvantage?
A. Slower than burst mode
B. CPU halted
C. Polling required
D. Cache disabled
Answer: A โ
78
Highest priority device serviced first โ technique?
A. Priority encoder / daisy chain
B. Memory
C. DMA
D. Cache
Answer: A โ
79
ISR saves CPU state โ restore after?
A. Resume interrupted program
B. DMA
C. Cache
D. Memory
Answer: A โ
80
Interrupt vector table size depends on:
A. Number of interrupt levels
B. Memory size
C. DMA
D. Cache
Answer: A โ
81
DMA reduces CPU cycles wasted in:
A. Programmed I/O
B. Interrupt-driven I/O
C. Polling only
D. Cache management
Answer: A โ
82
DMA transfer with bus width = 8 bytes, block = 2 KB โ number of transfers?
A. 256
B. 512
C. 1024
D. 2048
Answer: B โ
Solution: 2 KB = 2048 bytes โ bus 8 bytes โ 2048/8=256 transfers โ correct Answer: A โ
Wait careful: 2048/8=256 โ
Answer A
83
Vectored interrupt advantage โ ?
A. CPU fetches ISR directly
B. CPU polls devices
C. DMA
D. Cache
Answer: A โ
84
Nested interrupts allowed โ CPU must:
A. Save registers & PC
B. DMA only
C. Cache flush
D. Poll devices
Answer: A โ
85
Interrupt mask register โ function?
A. Enable/disable individual interrupts
B. Store data
C. DMA transfer
D. Cache
Answer: A โ
86
I/O device signals CPU โ method?
A. Interrupt
B. Polling
C. DMA
D. Cache
Answer: A โ
87
CPU executes EI instruction โ effect?
A. Enable interrupts
B. Disable
C. NOP
D. DMA transfer
Answer: A โ
88
CPU executes DI โ effect?
A. Disable interrupts
B. Enable
C. NOP
D. Cache flush
Answer: A โ
89
DMA reduces CPU involvement โ which mode?
A. All DMA modes
B. Only burst
C. Only cycle stealing
D. Polling
Answer: A โ
90
CPU polling I/O continuously โ main disadvantage?
A. Wastes CPU cycles
B. Faster I/O
C. Reduces memory
D. Reduces bus traffic
Answer: A โ
91
DMA transfer time depends on:
A. Bus width, block size, memory speed
B. Cache size only
C. Stack pointer
D. CPU only
Answer: A โ
92
DMA controller โ main registers?
A. Source, destination, count, control
B. Stack pointer
C. PC
D. Cache
Answer: A โ
93
CPU halted for single bus cycle during DMA โ type?
A. Cycle stealing
B. Burst mode
C. Polling
D. Programmed I/O
Answer: A โ
94
CPU halted for entire DMA block โ type?
A. Burst mode
B. Cycle stealing
C. Programmed I/O
D. Polling
Answer: A โ
95
Daisy chain priority โ first device โ
A. Highest priority
B. Lowest
C. Random
D. Disabled
Answer: A โ
96
DMA transfer complete โ CPU notified by:
A. Interrupt
B. Polling
C. Cache
D. Stack
Answer: A โ
97
Memory-mapped I/O โ address space?
A. Shared with memory
B. Separate
C. Only DMA
D. None
Answer: A โ
98
Isolated I/O โ address space?
A. Separate
B. Shared with memory
C. Cache
D. DMA
Answer: A โ
99
Interrupt service routine โ restores CPU state โ why?
A. Resume execution
B. DMA transfer
C. Cache flush
D. Polling
Answer: A โ
100
CPU halted for bus access during DMA โ mode?
A. Cycle stealing
B. Burst mode
C. Polling
D. Programmed I/O
Answer: A โ
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