Datapath and Control Unit — 100 MCQs (with solutions)
1
In a single-cycle MIPS datapath the ALU input B can come from either register file or an immediate extended sign. Which control signal selects the immediate for ALU input B?
A. RegDst
B. ALUSrc
C. MemtoReg
D. Branch
Answer: B
Solution: ALUSrc (1 → immediate/zero-extended used, 0 → register file second operand). RegDst selects destination register; MemtoReg selects writeback from memory vs ALU; Branch selects branch logic.
2
A 5-stage pipeline has stage latencies: IF=200 ps, ID=150 ps, EX=250 ps, MEM=200 ps, WB=100 ps. What is the clock period if no pipeline register overhead is included?
A. 250 ps
B. 200 ps
C. 1000 ps
D. 150 ps
Answer: A
Solution: In pipeline, clock period = max(stage delay). Max among (200,150,250,200,100) = 250 ps (EX). So clock period = 250 ps.
3
In the multicycle MIPS datapath, which component performs sign-extension of immediate fields?
A. ALU
B. Sign-extend unit fed from instruction field
C. Control unit microstore
D. Data memory
Answer: B
Solution: Immediate fields are sign-extended in a dedicated sign-extend unit in datapath, producing operand for ALU or address calculation.
4
Which control implementation uses a PLA or combinational logic to generate control signals every cycle based on opcode and status bits?
A. Microprogrammed control
B. Hardwired control
C. Tomasulo scheduling
D. Dynamic translation
Answer: B
Solution: Hardwired control uses combinational logic (often encoded in PLA) to produce control signals directly — fast, but less flexible. Microprogrammed control uses control memory and microinstructions.
5
In a 32-bit instruction set the register file has 32 registers. How many bits are required to encode a register specifier?
A. 4
B. 5
C. 6
D. 3
Answer: B
Solution: Need log₂(32) = 5 bits per register specifier.
6
In a pipelined processor, a RAW hazard occurs when:
A. An instruction writes a register after a following instruction reads it.
B. An instruction reads a register that is later written by earlier instruction.
C. Two instructions write same register simultaneously.
D. Instruction tries to read memory while another writes a different location.
Answer: B
Solution: RAW (read after write) hazard: consumer reads before producer writes result; occurs when dependent instruction reads register before prior instruction writes it.
7
Which hardware mechanism resolves RAW hazards without stalling in many pipelines?
A. Branch prediction
B. Forwarding (bypassing) paths and hazard detection logic
C. Reorder buffer
D. Cache coherence
Answer: B
Solution: Forwarding supplies ALU result directly to dependent instruction inputs prior to writeback, avoiding stalls.
8
Consider a 5-stage pipeline where an instruction producing an ALU result writes it in WB stage (stage 5). An immediately following dependent instruction needs that value in EX stage (stage 3). How many cycles of stall are needed if no forwarding is available?
A. 0
B. 1
C. 2
D. 3
Answer: C
Solution: Producer writes in cycle of WB (stage 5). Consumer needs value in its EX (stage 3). With pipeline overlap, without forwarding consumer must wait until producer completes WB before it can read in ID→EX; this requires 2 stall cycles (standard: immediate dependent without forwarding = 2-cycle stall for load? For ALU result produced in EX, with no forwarding need to stall 2 cycles). So 2.
9
A load-use hazard occurs when a load is followed by an instruction that uses loaded value immediately. In a classic 5-stage MIPS pipeline with simple forwarding and no special load forwarding, the required stall cycles are typically:
A. 0
B. 1
C. 2
D. 3
Answer: B
Solution: Load value available only after MEM stage; dependent instruction needs it in EX — with simple forwarding we still require 1 bubble (stall) between load and dependent use.
10
In a microprogrammed control unit, the microinstructions are stored in
A. Control store (ROM/ROM-like memory)
B. Register file
C. ALU
D. Data cache
Answer: A
Solution: Microinstructions live in control store (microprogram memory) which can be ROM/PLRAM; read by microsequencer.
11
A finite-state machine control implements instruction fetch control. What are typical FSM states for fetch sequence in a multicycle CPU?
A. IFETCH, DECODE, EXECUTE, MEMORY, WRITEBACK
B. T0 only
C. Single state only
D. None
Answer: A
Solution: Multicycle control often has states reflecting micro-steps per instruction: IF (fetch), ID (decode), EX (execute), MEM (memory access), WB (writeback), etc.
12
Consider a 4-stage pipelined processor with stages: IF (300 ps), ID (200 ps), EX (300 ps), MEM/WB combined (400 ps). If pipeline registers add 20 ps per stage boundary, what is clock period?
A. 420 ps
B. 320 ps
C. 300 ps
D. 400 ps
Answer: A
Solution: Stage delays + pipeline register overhead (must include per stage). Clock period = max(stage_delay + reg_overhead). Largest stage is MEM/WB 400 ps; add pipeline reg overhead 20 ps → 420 ps.
13
In control unit design, what does the microsequencer do?
A. Select next microinstruction address (via fields like next address, branch, or table)
B. Execute ALU operations
C. Access data cache
D. Manage TLB entries
Answer: A
Solution: Microsequencer computes next microaddress (sequential, branch, conditional, return-from-microroutine, etc.) based on microinstruction fields and status bits.
14
In a multicycle datapath, which control signal causes the register file to write back the result from ALU or memory?
A. RegWrite (enable)
B. MemWrite
C. Branch
D. ALUSrc
Answer: A
Solution: RegWrite enables writing to register file; MemWrite writes memory. MemtoReg selects source of data (memory or ALU).
15
A hardwired control unit with PLA expansion for opcode decode grows how (roughly) as instruction set size increases?
A. Linearly in number of instructions × control signals
B. Exponentially in bits
C. Constant
D. Sub-linear
Answer: A
Solution: PLA size (rows × columns) grows roughly linearly with number of decoded patterns and control signals.
16
Which structure supports dynamic scheduling and out-of-order execution by renaming registers and buffering results?
A. Tomasulo’s algorithm (reservation stations)
B. Static single assignment (SSA) only
C. Simple scoreboard-less pipeline
D. Branch target buffer
Answer: A
Solution: Tomasulo uses reservation stations, register renaming and a common data bus to enable out-of-order execution and avoid WAR/WAW hazards.
17
A scoreboard resolves hazards in floating point unit by tracking functional unit status. What hazards does it prevent versus which it permits?
A. Prevents RAW, handles WAW/WAR via scoreboarding (prevents WAW and WAR by waiting)
B. Prevents all hazards without stalls
C. Only structural hazards
D. None
Answer: A
Solution: Scoreboard enforces RAW dependences and checks for WAW/WAR and structural hazards, stalling when necessary to prevent WAW/WAR.
18
In a datapath that implements branch-and-link (call) which control action must occur?
A. Store return PC into link register and PC ← branch target
B. Only update PC
C. Only store return address
D. Flush caches
Answer: A
Solution: Branch-and-link must save return address (in link register or stack) and change PC to branch target.
19
Microinstructions typically include fields for next microaddress, micro-operations, and condition bits. Which field directs conditional branching within microprogram?
A. Condition code / test bits and next state selection multiplexer
B. ALU result directly
C. Cache index
D. None
Answer: A
Solution: Microinstruction contains condition bits and next-address selection logic — based on flags and conditions it chooses next microaddress.
20
In a multicycle datapath, an instruction fetch takes one cycle; decode takes second; an ALU op uses a third; memory read/write occurs in fourth; writeback in fifth. How many cycles does a load instruction take?
A. 5 cycles
B. 1 cycle
C. 3 cycles
D. 2 cycles
Answer: A
Solution: Load needs fetch, decode, ALU (address calc), MEM read, WB → 5 cycles in classical multicycle design.
21
In a pipeline, a structural hazard arises when:
A. Two instructions need same hardware resource in same cycle (e.g., single memory for instruction & data)
B. Data dependence causes RAW hazard
C. Branch misprediction happens
D. Register file has enough ports
Answer: A
Solution: Structural hazards are resource conflicts; e.g., single-ported memory used for both instruction fetch and data access.
22
A pipelined processor stalls for one cycle due to a bubble insertion. Which control unit component asserts the pipeline stall?
A. Hazard detection unit
B. ALU control only
C. Register file decoder
D. Memory controller
Answer: A
Solution: Hazard detection unit detects hazards (load-use, structural) and stalls pipeline registers accordingly.
23
Consider a datapath with register file writeback occurring in the first half of clock and read in second half; the WR and RD ports are in same cycle. Which hardware feature allows read-after-write in same cycle?
A. Write-first (read-after-write) register file (write port before read port)
B. Separate memory for read/write only
C. Forwarding bus needed
D. None
Answer: A
Solution: Register file with write-before-read (write occurs earlier in cycle) allows reading new value in same cycle.
24
During microprogramming, what is vertical microcode?
A. Compact microinstruction encoding with fields specifying micro-ops (high density)
B. Microcode with one micro-op per bit only
C. Microcode stored column-wise physically
D. Microcode for vertical processors only
Answer: A
Solution: Vertical microcode uses encoded fields (small width) — compact but needs additional decoding; horizontal is wide, one-hot micro-ops.
25
What is the tradeoff of horizontal versus vertical microinstructions?
A. Horizontal: wide, direct control of signals (faster, larger control store). Vertical: compact (smaller store), needs microdecoder (slower).
B. No tradeoff
C. Vertical always better
D. Horizontal always worse
Answer: A
Solution: Horizontal microinstrs give parallel control signals (fast), but use more bits; vertical saves space but requires decoding.
26
Control store address bits must at least cover the number of microinstructions. If a control store contains 2048 microinstructions, how many address bits are needed?
A. 11
B. 10
C. 12
D. 9
Answer: A
Solution: log₂(2048)=11 → need 11 address bits.
27
Which of below best describes microprogrammed control advantage?
A. Flexibility – instruction set changes simple by changing microcode
B. Always faster than hardwired control
C. Uses no control memory
D. Eliminates hazards
Answer: A
Solution: Microprogramming enables ISA changes and easier implementation of complex instructions, though generally slower.
28
In a pipelined CPU a branch is resolved in ID stage (early decode). Which penalty is likely when branch taken?
A. Flush of IF stage instruction (1-cycle penalty)
B. Immediate continue with no penalty
C. Two memory writes
D. Register file corruption
Answer: A
Solution: If branch decision occurs in ID, instruction fetched in IF of next cycle likely wrong and must be flushed — 1 cycle penalty.
29
Consider a pipelined datapath with forwarding. Which case still requires a stall even with full forwarding?
A. Load-use (load followed immediately by dependent instruction)
B. ALU result followed by dependent
C. Two independent instructions
D. Branch resolved in EX
Answer: A
Solution: Load value is available only after MEM stage; even with forwarding, immediate dependent needs value earlier → requires one stall.
30
Suppose you design a control FSM with 8 states. You implement next-state logic as a combinational function of current state and inputs. If you want to reduce state count via microcode, which technique applies?
A. Microsequencing with conditional microinstructions to share micro-steps across opcodes
B. Increase state bits
C. Add more hardware only
D. None
Answer: A
Solution: Microsequencing and microprogramming can reduce explicit FSM states by encoding behavior in microinstructions and using conditional sequencing.
31
Branch delay slots are used to fill pipeline bubble with useful instruction. If one delay slot exists after branch, and branch is unconditional, how many instructions after branch are executed regardless of branch?
A. 1 instruction (the delay slot)
B. 0
C. 2
D. All following instructions
Answer: A
Solution: One delay slot executed after branch before branch effect; so single instruction executes regardless.
32
In a data path, ALUop control field (2 bits) together with function field (6 bits) generate final ALU control lines. Which unit performs final decode into ALU control?
A. ALU Control (small combinational decoder)
B. Main control only
C. Register file
D. Memory
Answer: A
Solution: ALU control combines ALUOp with instruction function field to produce ALU control signals.
33
If a control store uses 64-bit microinstructions and has 4096 entries, how many bits total storage is required?
A. 262,144 bits
B. 512,000 bits
C. 64 × 4096 = 262,144 bits → yes
D. 128,000 bits
Answer: C
Solution: 64 bits × 4096 entries = 262,144 bits.
34
A control unit must sequence a shift-and-add multiply that requires 16 iterations for 16-bit operands. Implementing multiply as microcode vs hardwired FSM: which is generally smaller microcode-wise?
A. Microcode smaller because loop encoded once and iterated (uses fewer microinstructions than full unrolled FSM)
B. Hardwired always smaller
C. Both same
D. None
Answer: A
Solution: Microcode can reuse loop microinstructions and conditional branch, reducing control store footprint vs unrolled hardwired FSM.
35
In Tomasulo’s algorithm, the Common Data Bus (CDB) carries:
A. Result values and tags to waiting reservation stations
B. Program counter only
C. Control store signals
D. Memory addresses
Answer: A
Solution: CDB broadcasts computed results and tags so dependent reservation stations and register file entries can capture results and clear tags.
36
A datapath uses register renaming. Which hazards are eliminated by renaming?
A. WAR and WAW hazards (not RAW)
B. RAW only
C. All hazards
D. None
Answer: A
Solution: Register renaming gives unique physical registers for logical destination registers eliminating WAW and WAR; RAW remains.
37
In a single-cycle datapath the cycle time must accommodate the longest instruction end-to-end. What is the main disadvantage?
A. Slow clock (long cycle time) because memory access, ALU, and register write all in one cycle
B. Complexity lessened
C. Multiple clocks faster
D. None
Answer: A
Solution: Single-cycle forces long cycle to accommodate slowest instruction → poor performance.
38
Which control flow is typical in microinstructions to implement conditional jump on zero flag?
A. NextMicroAddr = (Zero ? branchMicroAddr : nextSeqAddr)
B. Next = next + 1 only
C. Ignore flags
D. None
Answer: A
Solution: Microsequencer checks condition flags and selects next microaddress accordingly.
39
A pipelined processor uses scoreboard and Tomasulo. Which allows out-of-order issue and completion while preserving precise exceptions more easily?
A. Tomasulo with reorder buffer (ROB)
B. Scoreboard only
C. Simple pipeline
D. None
Answer: A
Solution: Tomasulo with ROB allows out-of-order execution and in-order retirement, facilitating precise exceptions.
40
When implementing branches, which hardware computes target address in a pipelined CPU to minimize stall?
A. Branch target buffer (BTB) and branch adder in IF stage
B. Use only ID stage to compute target
C. Compute after MEM stage
D. None
Answer: A
Solution: BTB stores predicted target and branch adder in IF helps fetch target early, reducing penalty.
41
For control FSM with 16 states, encoded in binary, how many flip-flops are needed to hold the state?
A. 4
B. 16
C. 8
D. 5
Answer: A
Solution: Need log₂(16)=4 state bits → 4 flip-flops.
42
Suppose ALU result is produced at end of EX stage, and forwarding path EX→EX is available, but MEM→EX forwarding is not. For instruction sequence: ADD r1,r2,r3 (produces in EX), SUB r4,r1,r5 (uses r1 in EX next cycle), will forwarding resolve hazard?
A. Yes — EX→EX forwarding supplies result to next EX stage
B. No — stall required because MEM→EX missing
C. Only if pipeline flushes
D. None
Answer: A
Solution: Producer ALU result available at end of EX and can be forwarded to operand input of the following EX stage via EX→EX path.
43
Which microarchitecture component typically stores the program counter and provides next sequential PC?
A. PC register with adder increment by 4 (word-size)
B. Register file
C. Control store
D. TLB
Answer: A
Solution: PC register plus incrementer/adder yields next sequential instruction address.
44
In a pipeline with branch prediction and 2-cycle penalty on mispredict, what is effect of improving branch predictor accuracy from 90% to 95% if 20% of instructions are branches? CPI base 1? (Assume perfect otherwise and one mispredict cost = 2 cycles lost per mispredicted branch)
A. Compute mispredict rate: 10%→5% of branches. Branch fraction 0.2 so mispred per instruction: 0.2×0.10=0.02 → penalty = 0.02×2 =0.04 cycles. New: 0.2×0.05=0.01→ penalty 0.02. CPI increase reduced from 0.04 to 0.02 → CPI improvement 0.02. Which option matches?
A. CPI reduced by 0.02
B. CPI reduced by 0.04
C. CPI no change
D. CPI increased
Answer: A
Solution: See calculation above: improvement reduces mispredict penalty by 0.02 cycles per instruction.
45
A control unit must implement an instruction that uses memory indirect addressing requiring two memory accesses inside one instruction. Which control approach handles this more easily?
A. Microprogrammed control (because multiple micro-steps are convenient)
B. Hardwired only
C. No control required
D. None
Answer: A
Solution: Microprogramming eases multi-step complex instruction implementations.
46
In a pipelined MIPS, exceptions must be precise. Which technique helps maintain precise exceptions in out-of-order cores?
A. Reorder buffer (ROB) to retire instructions in program order
B. Scoreboard alone
C. No mechanism — exceptions imprecise
D. Branch predictor only
Answer: A
Solution: ROB ensures instructions commit in program order, enabling precise exceptions.
47
Consider microinstruction width 128 bits (horizontal) and 8192 microinstructions. How large control store in bytes?
A. 128 bits × 8192 = 1,048,576 bits = 131,072 bytes → compute: 128*8192=1,048,576 bits; /8 = 131,072 bytes.
B. 64KB
C. 2MB
D. 16KB
Answer: A
Solution: Calculation shown: 1,048,576 bits = 131,072 bytes (~128 KB).
48
A multicycle control uses an internal register IR that holds instruction. Which micro-step uses IR bits to select next control path?
A. Decode micro-step (examines opcode and funct)
B. Fetch micro-step only
C. Memory stage only
D. None
Answer: A
Solution: During decode, opcode and function fields in IR are used to determine instruction class and control sequencing.
49
Which control signal must be asserted to store data into data memory?
A. MemWrite
B. MemRead
C. RegWrite
D. ALUSrc
Answer: A
Solution: MemWrite enables writing data to memory.
50
If a hardware control unit uses microprogram ROM (read-only) but wants patchability, which approach is practical?
A. Use ROM shadowed by writable RAM (control store RAM) with initial contents from ROM and allow patches in RAM
B. ROM cannot be patched at all
C. Use only hardwired logic
D. None
Answer: A
Solution: Many systems use writable control store (RAM) that can be loaded at boot (shadowing ROM) to allow microcode updates.
Excellent ✅ — here’s Set 2 (Questions 51–100) on Datapath and Control Unit from Computer Organization & Architecture (GATE level).
Each question is plagiarism-free, conceptually tough, and includes detailed explanations.
51.
A processor uses a 3-stage pipeline (IF, EX, WB). The stage delays are 120 ps, 180 ps, and 100 ps respectively. The register overhead is 20 ps. What is the minimum clock period?
A. 200 ps
B. 220 ps
C. 180 ps
D. 300 ps
Answer: B
Solution:
Clock period = Max(stage delay) + pipeline register overhead = 180 + 20 = 200 ps.
But since register overhead applies at every boundary, total effective stage time = 200 ps minimum. Option B (200 ps).
52.
In a single-cycle datapath, what happens if the memory access takes longer than ALU operation?
A. The CPU clock slows down to match memory delay
B. Memory access occurs asynchronously
C. Instruction is skipped
D. Control signals are ignored
Answer: A
Solution:
Single-cycle processors complete all operations in one clock. The clock must be as long as the slowest operation (typically memory). Hence, clock period is governed by memory delay.
53.
The microprogram counter (μPC) in a microprogrammed control unit functions similar to:
A. Program Counter (PC) of main instruction cycle
B. Memory Data Register
C. Status register
D. Condition code
Answer: A
Solution:
The microprogram counter (μPC) keeps the address of the next microinstruction, just like the PC stores the address of the next macro-instruction.
54.
A hardwired control unit is faster than a microprogrammed control unit because:
A. It uses fixed combinational circuits
B. It executes microinstructions
C. It supports more instructions
D. It has a smaller control store
Answer: A
Solution:
Hardwired control directly generates signals via logic circuits (PLA), avoiding memory lookup delays from microcode.
55.
Which of the following statements is true about microprogrammed control?
A. It is slower but flexible
B. It is faster but inflexible
C. It eliminates hazards
D. It uses no sequencing
Answer: A
Solution:
Microprogramming trades speed for flexibility — ISA changes or complex operations can be modified via microcode without changing hardware.
56.
In the datapath of a MIPS-like CPU, the control signal MemtoReg is asserted when:
A. The result should be read from memory to a register
B. The result should come from the ALU
C. A branch is taken
D. An immediate value is needed
Answer: A
Solution:MemtoReg = 1 routes memory output to the register write-back input. For ALU results, MemtoReg = 0.
57.
What is the function of the Control Word (CW) in microprogrammed control?
A. It defines all control signals for a given micro-operation
B. It stores data operands
C. It holds ALU outputs
D. It stores program counter
Answer: A
Solution:
A Control Word is a bit-field encoding all micro-operations (control signals) that execute in one microinstruction cycle.
58.
Which of the following microinstruction formats leads to maximum parallelism?
A. Horizontal microinstruction
B. Vertical microinstruction
C. Compact encoded format
D. None
Answer: A
Solution:
Horizontal microinstructions assign one bit per control line → multiple micro-operations executed simultaneously.
59.
In a hardwired control design, which of the following increases complexity exponentially?
A. Number of instructions and addressing modes
B. Number of ALU control lines only
C. Memory bandwidth
D. Data bus width
Answer: A
Solution:
Hardwired logic complexity grows rapidly with instruction count and addressing modes due to multiple condition decoding paths.
60.
If a pipeline has 5 stages, and the first instruction enters at cycle 1, the fifth instruction completes at which cycle (assuming ideal pipeline)?
A. 9
B. 5
C. 6
D. 7
Answer: D
Solution:
First instruction completes at cycle 5; each subsequent completes one per cycle.
→ Instruction 5 completes at cycle 9. Wait: 5 stages = latency 5 cycles → first result at cycle 5, second at 6, third 7, fourth 8, fifth 9 → Answer: A (9).
61.
In a pipeline with no forwarding, the instruction sequence:
I1: ADD R1, R2, R3
I2: SUB R4, R1, R5requires how many stall cycles?
A. 1
B. 2
C. 3
D. 0
Answer: B
Solution:I1 produces R1 after WB (stage 5). I2 needs it in EX (stage 3). So, 2-cycle stall required.
62.
In a microprogrammed control, which field defines the address of the next microinstruction?
A. Next-address field
B. Control field
C. Data field
D. None
Answer: A
Solution:
Microinstructions include a next-address field for sequencing control flow (conditional or sequential).
63.
A microsequencer uses condition bits (e.g., zero flag). Which component evaluates these?
A. Condition logic circuitry
B. ALU
C. Memory unit
D. Decoder
Answer: A
Solution:
Condition logic reads CPU flags and determines the next microinstruction address based on test results.
64.
The control memory in a microprogrammed control unit is similar to:
A. ROM
B. Cache
C. RAM
D. Stack
Answer: A
Solution:
Control memory (microstore) is typically implemented as ROM (fixed microcode).
65.
In a multicycle datapath, a load word (LW) instruction requires how many cycles typically?
A. 5
B. 4
C. 3
D. 2
Answer: A
Solution:
LW: IF (1), ID (2), EX (3), MEM (4), WB (5). Total = 5 cycles.
66.
What is the main function of control signals in datapath?
A. To coordinate movement and operation of data
B. To store immediate values
C. To manage interrupts
D. To synchronize cache operations
Answer: A
Solution:
Control signals activate datapath components (e.g., ALU, MUX, register file) for correct instruction execution.
67.
Which unit controls branch instruction decision in pipeline?
A. Branch Control Unit (part of EX or ID stage)
B. Memory controller
C. Reorder buffer
D. Data cache
Answer: A
Solution:
Branch Control logic in ID/EX stage compares register values and sets PC accordingly.
68.
A control word is 32 bits wide, and there are 256 microinstructions. What is the total control memory size?
A. 8192 bits
B. 8192 bytes
C. 4096 bits
D. 1024 bytes
Answer: B
Solution:
32 × 256 = 8192 bits = 1024 bytes (not 8192 bytes). So correct is D (1024 bytes).
69.
The control unit that implements conditional microbranching uses which hardware element?
A. Microsequencer
B. ALU
C. Data memory
D. Decoder only
Answer: A
Solution:
Microsequencer checks condition bits and selects next microaddress.
70.
What is the major advantage of hardwired control over microprogrammed control?
A. Faster instruction decoding and execution
B. Flexibility
C. Easier debugging
D. Simpler design
Answer: A
Solution:
Hardwired control provides speed advantage because no microinstruction memory fetch is required.
71.
A pipeline has a CPI (cycles per instruction) of 1.0 ideally. If 10% instructions cause one-cycle stall, what is effective CPI?
A. 1.10
B. 1.01
C. 1.2
D. 0.9
Answer: A
Solution:
CPI = 1 + (0.10 × 1) = 1.10.
72.
In microprogrammed control, microinstructions are executed:
A. Sequentially, unless a branch occurs
B. Out-of-order
C. Randomly
D. Asynchronous
Answer: A
Solution:
Microinstructions execute sequentially, unless conditional or unconditional branch occurs.
73.
A microinstruction that activates multiple independent operations in a single cycle is known as:
A. Horizontal microinstruction
B. Compact microinstruction
C. Vertical microinstruction
D. Serial microinstruction
Answer: A
Solution:
Horizontal microcode allows simultaneous control of independent operations.
74.
In control unit design, control signal generation from instruction opcode is achieved through:
A. Decoder logic
B. ALU
C. Cache controller
D. DMA unit
Answer: A
Solution:
Instruction opcode is decoded via combinational logic/PLA to generate control signals.
75.
Which microinstruction type provides maximum parallelism and minimum control memory utilization tradeoff?
A. Mixed (hybrid) microinstruction
B. Vertical
C. Horizontal
D. Linear
Answer: A
Solution:
Hybrid microinstructions mix encoded and direct fields to balance speed and storage.
76.
If ALU requires 2 ns, memory 3 ns, and control decoding 1 ns in a single-cycle datapath, the total minimum clock period = ?
A. 3 ns
B. 4 ns
C. 6 ns
D. 7 ns
Answer: C
Solution:
Total = max of sequential path = 2 + 3 + 1 = 6 ns.
77.
In pipelining, control hazard can be minimized by:
A. Branch prediction and delay slots
B. Increasing cache
C. Reducing ALU delay
D. Data forwarding
Answer: A
Solution:
Control hazards occur due to branches → reduced by prediction or delay slots.
78.
A microinstruction that explicitly states all control signals without encoding is called:
A. Horizontal microinstruction
B. Vertical microinstruction
C. Subroutine microcode
D. Minimal microcode
Answer: A
Solution:
Horizontal microinstruction directly specifies control signals (no decoding).
79.
A hardwired control using PLA has 64 inputs and 128 outputs. How many minterms possible?
A. 2⁶⁴
B. 64 × 128
C. 128²
D. 64²
Answer: A
Solution:
PLA maps inputs to outputs using AND-OR arrays; input combinations = 2⁶⁴ possible patterns.
80.
The control signals required for MIPS ‘R-type’ ALU instruction include:
A. RegDst=1, RegWrite=1, ALUSrc=0, MemtoReg=0
B. RegDst=0, MemWrite=1
C. Branch=1, Jump=1
D. MemtoReg=1
Answer: A
Solution:
R-type ALU: destination in rd, from ALU, register operands → hence given signals true.
81.
A pipeline increases throughput primarily by:
A. Overlapping instruction execution
B. Reducing instruction latency
C. Increasing clock delay
D. Increasing hardware hazards
Answer: A
Solution:
Pipeline improves throughput via overlapping of multiple instructions.
82.
The Control Store in microprogrammed control is addressed by:
A. Microprogram counter
B. ALU output
C. Main memory
D. Instruction register directly
Answer: A
Solution:
Control store uses microprogram counter to fetch next microinstruction.
83.
Which type of microinstruction representation reduces control store size most?
A. Vertical
B. Horizontal
C. Hybrid
D. Parallel
Answer: A
Solution:
Vertical microinstructions use encoded control fields, reducing store width.
84.
The execution time per instruction in an n-stage pipeline (ignoring stalls) is approximately:
A. (T_clock)
B. n × T_clock
C. (T_clock / n)
D. Constant
Answer: A
Solution:
Each instruction completes every cycle (throughput = 1/Tclock). So execution time ≈ Tclock.
85.
A microinstruction field with value 1010 selects operation code. What unit decodes this?
A. Micro-operation decoder
B. Main decoder
C. Memory unit
D. ALU
Answer: A
Solution:
Micro-op decoder interprets encoded fields from microinstruction into control signals.
86.
Control hazards in pipelining are caused by:
A. Branches and jumps
B. Cache misses
C. ALU overflow
D. Data dependencies
Answer: A
Solution:
Control hazards occur due to change in instruction flow (branch, jump).
87.
A datapath uses a 2-to-1 MUX to choose between register data and immediate operand. Which control line selects input?
A. ALUSrc
B. RegDst
C. MemtoReg
D. Branch
Answer: A
Solution:
ALUSrc decides ALU’s second input: register (0) or immediate (1).
88.
Microprogrammed control can be patched using:
A. Writable Control Store (RAM-based)
B. ROM-only control
C. PLA-based logic
D. Cache
Answer: A
Solution:
Writable Control Store allows microcode modification for bug fixes or ISA updates.
89.
In a pipelined processor, pipeline registers are used to:
A. Hold intermediate results between stages
B. Buffer data cache
C. Increase memory
D. Store microcode
Answer: A
Solution:
Pipeline registers isolate stages, maintaining stage outputs between cycles.
90.
The control unit responsible for instruction sequencing uses:
A. FSM (Finite State Machine)
B. Memory controller
C. ALU decoder
D. Cache
Answer: A
Solution:
Instruction sequencing is modeled using FSM or microprogram sequencing logic.
91.
A microinstruction cycle time of 100 ns and 20 microinstructions per instruction gives instruction time:
A. 2 µs
B. 200 ns
C. 1 µs
D. 0.5 µs
Answer: A
Solution:
Time per instruction = 20 × 100 ns = 2000 ns = 2 µs.
92.
A control memory has 2K words, each 32 bits wide. Total capacity = ?
A. 64 Kbits
B. 8 Kbits
C. 2 Kbits
D. 16 Kbits
Answer: A
Solution:
2K × 32 = 2048 × 32 = 65,536 bits = 64 Kbits.
93.
Tomasulo’s algorithm helps eliminate which type of pipeline hazards?
A. WAW and WAR
B. Structural only
C. RAW
D. None
Answer: A
Solution:
Tomasulo dynamically renames registers → removes WAW & WAR hazards.
94.
Scoreboarding was introduced first in:
A. CDC 6600
B. Intel 8086
C. IBM 360
D. Pentium Pro
Answer: A
Solution:
Scoreboarding technique for dynamic scheduling introduced in CDC 6600 (1964).
95.
The Branch Target Buffer (BTB) stores:
A. Target addresses of recently executed branches
B. Instruction operands
C. Opcode mappings
D. Cache lines
Answer: A
Solution:
BTB caches branch target addresses for faster prediction.
96.
A pipeline improves:
A. Throughput
B. Latency
C. Both equally
D. None
Answer: A
Solution:
Pipeline increases throughput but not single instruction latency.
97.
A control store with 8-bit microinstruction address can store how many microinstructions?
A. 256
B. 128
C. 512
D. 64
Answer: A
Solution:
2⁸ = 256 microinstructions.
98.
A microprogrammed control requires how many microinstructions for an instruction taking 4 cycles?
A. 4
B. 8
C. 2
D. 1
Answer: A
Solution:
Each micro-step = one microinstruction → 4 cycles → 4 microinstructions.