I/O Interface, Interrupts, and DMA Mode MCQs
I/O Interface, Interrupts, and DMA Mode MCQs 1 In programmed I/O, the CPU waits until the I/O operation is complete. …
Computer Organization and Architecture
Memory Hierarchy: Cache, Main Memory, Secondary Storage MCQs for Gate exam
Memory Hierarchy: Cache, Main Memory, Secondary Storage MCQs for Computer Organization and Architecture 1 A computer has a cache hit …
Instruction Pipelining and Pipeline Hazards MCQs for Gate exam
Instruction Pipelining and Pipeline Hazards MCQs 1 A 5-stage instruction pipeline has stage delays: IF=200 ps, ID=150 ps, EX=250 ps, …
Datapath and Control Unit MCQs for Gate
Datapath and Control Unit — 100 MCQs (with solutions) 1 In a single-cycle MIPS datapath the ALU input B can …
ALU MCQs for Gate Exam
ALU MCQs for Gate Exam 1 (Two’s-complement addition / overflow)Add the 8-bit two’s-complement numbers 0x7A and 0x3C. Which is correct?A. …
Machine instructions and addressing modes MCQs For Gate
Machine Instructions and Addressing Modes (Computer Organization & Architecture) Each question has options A–D, the correct answer, and a detailed …