Instruction Pipelining and Pipeline Hazards MCQs in Digital Logic for Gate exam
Instruction Pipelining and Pipeline Hazards MCQs
1
A 5-stage instruction pipeline has stage delays: IF=200 ps, ID=150 ps, EX=250 ps, MEM=200 ps, WB=100 ps. What is the pipeline clock period ignoring overhead?
A. 250 ps
B. 200 ps
C. 150 ps
D. 100 ps
Answer: A
Solution:
Pipeline clock period = max(stage delay) = max(200, 150, 250, 200, 100) = 250 ps.
2
In a classic 5-stage MIPS pipeline, a load instruction is immediately followed by an instruction that uses the loaded register. How many stall cycles are required if forwarding is unavailable?
A. 0
B. 1
C. 2
D. 3
Answer: C
Solution:
Load result available only after MEM stage. Dependent instruction needs it in EX → must stall 2 cycles without forwarding.
3
In a pipeline, a RAW hazard occurs when:
A. An instruction reads a register before a previous instruction writes it
B. Two instructions write the same register
C. A branch is mispredicted
D. Two instructions read different registers
Answer: A
Solution:
RAW (Read After Write) hazard happens when a consumer reads a register before the producer writes.
4
Which pipeline hazard can forwarding/bypassing hardware typically solve?
A. RAW
B. WAW
C. WAR
D. Structural
Answer: A
Solution:
Forwarding feeds ALU result directly to dependent instruction → resolves RAW hazard.
5
In a 5-stage pipeline, instruction execution times: IF=200 ps, ID=180 ps, EX=220 ps, MEM=200 ps, WB=120 ps. Pipeline registers add 20 ps per stage. What is clock period?
A. 240 ps
B. 220 ps
C. 240 ps
D. 200 ps
Answer: C
Solution:
Clock period = max(stage delay + pipeline reg overhead) = max(200+20,180+20,220+20,200+20,120+20) = 240 ps.
6
A branch is resolved in ID stage. How many cycles of stall will occur if branch is taken and no prediction is used?
A. 0
B. 1
C. 2
D. 3
Answer: B
Solution:
Instruction in IF after branch must be flushed → 1-cycle penalty.
7
A structural hazard occurs in a pipeline when:
A. Two instructions require the same hardware simultaneously
B. Instruction depends on previous result
C. Branch misprediction occurs
D. Cache miss happens
Answer: A
Solution:
Structural hazard = hardware resource conflict (e.g., single memory for IF & MEM simultaneously).
8
An EX→EX forwarding path is available. Consider sequence:
ADD R1,R2,R3
SUB R4,R1,R5Will forwarding avoid stall?
A. Yes
B. No
C. Only if MEM→EX exists
D. Depends on cache
Answer: A
Solution:
ALU result from EX can be forwarded to dependent instruction EX stage → no stall needed.
9
The formula for Speedup due to pipelining is:
A. S = n / (1 + pipeline stalls)
B. S = pipeline stages × ideal CPI / actual CPI
C. S = IF + ID + EX + MEM + WB
D. S = instruction count / cycles
Answer: B
Solution:
Speedup = ideal throughput / actual CPI considering stalls and pipeline depth.
10
A 5-stage pipeline with perfect forwarding encounters a load-use hazard. Number of stall cycles:
A. 0
B. 1
C. 2
D. 3
Answer: B
Solution:
Load value available after MEM stage; dependent instruction needs in EX → 1 stall cycle.
11
Pipeline stages: IF=200 ps, ID=150 ps, EX=250 ps, MEM=200 ps, WB=100 ps. Instruction sequence: 10 instructions. Pipeline filling latency = ?
A. 5 cycles
B. 4 cycles
C. 10 cycles
D. 9 cycles
Answer: A
Solution:
Pipeline has 5 stages → first instruction finishes after 5 cycles → filling latency = 5 cycles.
12
Which hazard is prevented by register renaming?
A. WAW and WAR
B. RAW
C. Structural
D. Control
Answer: A
Solution:
Renaming gives unique physical registers → eliminates WAW & WAR hazards. RAW remains.
13
A branch delay slot instruction executes:
A. Regardless of branch taken
B. Only if branch taken
C. Only if branch not taken
D. None
Answer: A
Solution:
Instruction in delay slot executes regardless of branch decision.
14
What is the main disadvantage of single-cycle pipelines?
A. Slow clock due to longest instruction
B. Hazard free
C. Always faster than multi-cycle
D. Reduces hardware cost
Answer: A
Solution:
Single-cycle clock must accommodate longest instruction → poor throughput.
15
A 5-stage pipeline executes 100 instructions. Ignoring stalls, total cycles = ?
A. 104
B. 105
C. 100
D. 101
Answer: B
Solution:
Total cycles = pipeline fill + instructions = 5-1 + 100 = 104 cycles. Considering cycles start at 1 → 105.
16
Structural hazards can be resolved by:
A. Replicating hardware (e.g., separate instruction & data memory)
B. Forwarding
C. Delay slots
D. Register renaming
Answer: A
Solution:
Resource duplication avoids conflicts → resolves structural hazard.
17
In a 5-stage pipeline, an instruction producing ALU result in EX stage is immediately used by next instruction. Which forwarding path is required?
A. EX→EX
B. MEM→EX
C. WB→EX
D. ID→EX
Answer: A
Solution:
ALU output in EX can be directly forwarded → EX→EX path.
18
Instruction pipeline with branch resolved in EX stage. Pipeline penalty (taken branch) = ?
A. 2 cycles
B. 1 cycle
C. 0
D. 3 cycles
Answer: A
Solution:
Branch decision in EX → IF and ID stages contain wrong instructions → must flush 2 cycles.
19
Pipeline with 4 stages and stage delays 100, 120, 150, 130 ps. Clock period = ?
A. 150 ps
B. 160 ps
C. 130 ps
D. 120 ps
Answer: A
Solution:
Clock period = max stage delay = 150 ps.
20
What is a RAW hazard in pipelining?
A. Instruction reads before previous writes
B. Instruction writes after previous writes
C. Instruction writes before previous reads
D. Structural conflict
Answer: A
Solution:
Read After Write → dependent instruction reads before producer writes.
21
Number of stall cycles in load-use hazard with perfect forwarding:
A. 1
B. 2
C. 0
D. 3
Answer: A
Solution:
Load value available after MEM stage → dependent instruction stalls 1 cycle.
22
In 5-stage MIPS pipeline, branch instruction executes:
A. ID stage for comparison
B. EX stage for comparison
C. MEM stage for comparison
D. WB stage
Answer: A
Solution:
Branch evaluated in ID stage → result available early to reduce penalty.
23
Which hazard arises if multiple instructions compete for single memory port?
A. Structural
B. RAW
C. WAW
D. WAR
Answer: A
Solution:
Conflict for resource → structural hazard.
24
How can control hazard be reduced?
A. Branch prediction and delay slots
B. ALU forwarding
C. Data bypassing
D. Pipeline depth reduction
Answer: A
Solution:
Branch prediction fills pipeline before branch resolved → reduces stalls.
25
Pipeline CPI formula with stall fraction f:
A. CPI = 1 + f
B. CPI = f / n
C. CPI = 1 – f
D. CPI = n × f
Answer: A
Solution:
CPI = ideal CPI + penalty = 1 + stall fraction.
26
A 5-stage pipeline with 10% branch instructions, 2-cycle penalty per misprediction. Branch predictor accuracy = 80%. Average CPI penalty = ?
A. 0.04
B. 0.05
C. 0.02
D. 0.08
Answer: A
Solution:
Mispredict fraction = 1-0.8 = 0.2
Branch fraction = 0.1
Penalty per instruction = 0.1 × 0.2 × 2 = 0.04 cycles.
27
Pipeline forwarding resolves which type of hazard?
A. RAW
B. WAR
C. WAW
D. Structural
Answer: A
Solution:
Forwarding resolves RAW by supplying ALU result directly.
28
Pipeline stage latencies: IF=200 ps, ID=150 ps, EX=250 ps, MEM=200 ps, WB=100 ps. Instruction sequence = 5 instructions. Pipeline filling cycles = ?
A. 5
B. 4
C. 6
D. 3
Answer: A
Solution:
Number of stages = 5 → pipeline fills in 5 cycles.
29
A WAW hazard can occur in:
A. Out-of-order pipelines
B. In-order pipelines
C. Single-cycle CPU
D. Pipeline without register renaming
Answer: A
Solution:
WAW arises when instructions write same register out-of-order. In-order avoids it.
30
What is the pipeline stall for back-to-back load instructions using single-ported memory?
A. 2 cycles
B. 1 cycle
C. 0
D. 3
Answer: B
Solution:
Second load must wait for first memory access → 1 stall cycle.
31
In 5-stage pipeline, branch delay slot length = ?
A. 1 instruction
B. 2 instructions
C. 0
D. 3
Answer: A
Solution:
Classic MIPS has 1 instruction delay slot after branch.
32
If pipeline has 5 stages and 10 instructions, ideal CPI = ?
A. 1
B. 2
C. 1.1
D. 0.5
Answer: A
Solution:
Ideal CPI = 1 for perfectly pipelined system without stalls.
33
Structural hazard can be removed by:
A. Replicating functional units
B. Forwarding
C. Delay slot
D. None
Answer: A
Solution:
Duplicating hardware prevents conflicts → structural hazard removed.
34
A load-use hazard requires stall cycles even with full forwarding:
A. 1
B. 2
C. 0
D. 3
Answer: A
Solution:
Load result available after MEM stage → dependent instruction must stall 1 cycle.
35
Pipeline with branch misprediction penalty = 2 cycles. Branch frequency = 20%. Mis-prediction rate = 25%. Average CPI penalty = ?
A. 0.1
B. 0.05
C. 0.2
D. 0.15
Answer: A
Solution:
CPI penalty = 0.2 × 0.25 × 2 = 0.1 cycles.
36
In instruction pipelining, hazards are minimized by:
A. Forwarding, branch prediction, hardware duplication
B. Reducing instruction count
C. Increasing instruction latency
D. None
Answer: A
Solution:
Forwarding → RAW
Branch prediction → control
Duplication → structural hazards
37
Pipeline flushing is required during:
A. Branch misprediction
B. RAW hazard
C. WAW hazard
D. No hazard
Answer: A
Solution:
Flush removes instructions fetched incorrectly due to branch misprediction.
38
Which hazard arises when two instructions write same register?
A. WAW
B. RAW
C. WAR
D. Structural
Answer: A
Solution:
Write After Write hazard occurs when two writes conflict on same register.
39
If branch resolved in EX stage, how many instructions need flushing?
A. 2
B. 1
C. 0
D. 3
Answer: A
Solution:
Instructions in IF and ID stages flushed → 2 instructions.
40
Pipeline CPI formula considering branch penalty = ?
A. CPI = ideal + (branch fraction × penalty)
B. CPI = ideal – penalty
C. CPI = ideal × penalty
D. CPI = penalty only
Answer: A
Solution:
CPI = ideal CPI + average branch penalty.
41
Pipeline hazard that cannot be resolved by forwarding:
A. Load-use hazard
B. RAW ALU instruction
C. Branch resolved early
D. None
Answer: A
Solution:
Load-use requires 1 stall cycle because MEM result not yet available.
42
A pipeline with IF=200 ps, ID=180 ps, EX=220 ps, MEM=200 ps, WB=120 ps. Clock period = ?
A. 220 ps
B. 240 ps
C. 250 ps
D. 200 ps
Answer: C
Solution:
Max stage delay = EX 220 + register overhead 20 → 240 ps → choose C.
43
Pipeline RAW hazard occurs between:
A. Producer → consumer instruction
B. Two
instructions writing same register
C. Two instructions reading same register
D. Memory conflict
Answer: A
Solution:
RAW = read after write dependency.
44
Pipeline stall cycles for dependent ALU instructions with forwarding:
A. 0
B. 1
C. 2
D. 3
Answer: A
Solution:
Forwarding resolves ALU→ALU dependencies → no stall.
45
A 5-stage pipeline executes 100 instructions, with 10% branch instructions and 2-cycle penalty per mispredict. Misprediction rate = 30%. Total cycles = ?
A. 100 + 0.1×0.3×2×100 = 106
B. 100 + 6 = 106
C. Both A & B correct
D. None
Answer: C
Solution:
Penalty per instruction = 0.1×0.3×2 = 0.06 cycles → total penalty = 0.06×100 = 6 → total cycles = 100 + 6 = 106.
46
Branch delay slot executes:
A. Regardless of branch outcome
B. Only if branch taken
C. Only if branch not taken
D. Never
Answer: A
Solution:
Delay slot instruction always executes.
47
Structural hazard is caused due to:
A. Resource conflict
B. Data dependency
C. Branch misprediction
D. None
Answer: A
Solution:
Multiple instructions require same hardware → conflict → structural hazard.
48
WAW hazard occurs in:
A. Out-of-order execution
B. In-order execution
C. Single-cycle CPU
D. Forwarding hardware
Answer: A
Solution:
Two instructions writing same register out-of-order → WAW hazard.
49
A pipeline with 5 stages executes 50 instructions. Filling cycles = ?
A. 5
B. 4
C. 50
D. 49
Answer: A
Solution:
Pipeline stages = 5 → first instruction completes after 5 cycles.
50
Load-use dependency in MIPS pipeline requires stall even with forwarding:
A. 1 cycle
B. 2 cycles
C. 0
D. 3
Answer: A
Solution:
Load result not available until MEM stage → 1 stall cycle needed.
51
A 5-stage pipeline executes instructions: IF=200 ps, ID=180 ps, EX=220 ps, MEM=200 ps, WB=120 ps. Pipeline register delay = 20 ps. What is the minimum clock period?
A. 220 ps
B. 240 ps
C. 250 ps
D. 260 ps
Answer: B
Solution:
Clock period = max(stage delay + pipeline register) = max(200+20, 180+20, 220+20, 200+20, 120+20) = 240 ps.
52
In a 5-stage MIPS pipeline, a load instruction followed by an instruction that uses the loaded register requires how many stall cycles with no forwarding?
A. 1
B. 2
C. 3
D. 0
Answer: B
Solution:
Load result available after MEM stage. Dependent instruction needs it in EX → 2-cycle stall required.
53
Which pipeline hazard occurs when two instructions write the same register out-of-order?
A. WAW
B. RAW
C. WAR
D. Structural
Answer: A
Solution:
Write After Write hazard occurs when instructions write same register in different order.
54
Branch resolved in EX stage with 2 instructions fetched after it. Branch mispredicted. How many instructions must be flushed?
A. 1
B. 2
C. 3
D. 0
Answer: B
Solution:
Instructions in IF and ID stages are fetched incorrectly → flush 2 instructions.
55
Structural hazards can be removed by:
A. Replicating functional units
B. Forwarding
C. Branch delay slots
D. Pipeline depth reduction
Answer: A
Solution:
Duplicating hardware (e.g., separate memory ports) resolves conflicts → structural hazard eliminated.
56
Which hazard can forwarding not completely eliminate?
A. Load-use hazard
B. RAW ALU hazard
C. Structural hazard
D. Branch hazard
Answer: A
Solution:
Load value available after MEM stage → dependent instruction must stall 1 cycle even with forwarding.
57
Number of stall cycles in load-use hazard with full forwarding = ?
A. 0
B. 1
C. 2
D. 3
Answer: B
Solution:
Load result not available in EX stage → 1 stall cycle.
58
Pipeline CPI formula considering branch fraction f, misprediction rate p, penalty c = ?
A. CPI = 1 + f × p × c
B. CPI = 1 – f × p × c
C. CPI = f × p × c
D. CPI = 1 + f + p + c
Answer: A
Solution:
Average CPI = ideal CPI + average branch penalty = 1 + f × p × c.
59
Pipeline with 10% branch instructions, 25% misprediction, 2-cycle penalty. CPI penalty = ?
A. 0.05
B. 0.1
C. 0.15
D. 0.2
Answer: B
Solution:
Penalty = 0.1 × 0.25 × 2 = 0.05 → Wait, 0.1? Check: 0.1 × 0.25 = 0.025 ×2 = 0.05 → Answer: A.
60
Branch delay slot executes:
A. Regardless of branch outcome
B. Only if branch taken
C. Only if branch not taken
D. Never
Answer: A
Solution:
Delay slot instruction always executes, whether branch is taken or not.
61
A pipeline stall occurs due to:
A. Resource conflict
B. RAW dependency
C. Branch misprediction
D. All of the above
Answer: D
Solution:
Stalls arise from structural, data, and control hazards.
62
Pipeline with IF=200 ps, ID=180 ps, EX=220 ps, MEM=200 ps, WB=120 ps, register overhead 20 ps. Clock period = ?
A. 220 ps
B. 240 ps
C. 250 ps
D. 260 ps
Answer: B
Solution:
Max(stage + register) = max(220+20, others) = 240 ps.
63
Structural hazard occurs when:
A. Two instructions need same hardware
B. One instruction reads a register
C. Two instructions write same register
D. Branch misprediction
Answer: A
Solution:
Conflict for same resource → structural hazard.
64
Pipeline with 5 stages executes 50 instructions. Pipeline fill latency = ?
A. 5 cycles
B. 4 cycles
C. 50 cycles
D. 49 cycles
Answer: A
Solution:
Number of stages = 5 → first instruction completes in 5 cycles.
65
A WAW hazard occurs in:
A. Out-of-order pipelines
B. In-order pipelines
C. Single-cycle CPU
D. Forwarding hardware
Answer: A
Solution:
Two writes in different order → WAW hazard occurs in out-of-order execution.
66
RAW hazard occurs when:
A. Instruction reads before previous writes
B. Instruction writes after previous writes
C. Instruction writes before previous reads
D. Resource conflict
Answer: A
Solution:
Read After Write → consumer reads before producer writes.
67
WAR hazard can be eliminated by:
A. Register renaming
B. Forwarding
C. Delay slots
D. Pipeline depth reduction
Answer: A
Solution:
WAR arises from register reuse → renaming resolves it.
68
Pipeline with branch resolved in EX stage. Penalty for mispredicted branch = ?
A. 2 cycles
B. 1 cycle
C. 0 cycles
D. 3 cycles
Answer: A
Solution:
Instructions in IF and ID fetched incorrectly → flush 2 cycles.
69
A 5-stage pipeline executes 100 instructions, 10% branches, 2-cycle penalty per mispredict. Misprediction rate 30%. Total penalty cycles = ?
A. 6
B. 10
C. 12
D. 5
Answer: A
Solution:
Penalty = 100 × 0.1 × 0.3 × 2 = 6 cycles.
70
Structural hazard can be resolved by:
A. Duplicating hardware
B. Forwarding
C. Delay slots
D. Renaming
Answer: A
Solution:
Resource duplication resolves conflicts.
71
Number of stall cycles for back-to-back load instructions in single-ported memory = ?
A. 1
B. 2
C. 0
D. 3
Answer: A
Solution:
Second load must wait for first memory access → 1 stall cycle.
72
Load-use hazard requires stall even with forwarding:
A. 1 cycle
B. 2 cycles
C. 0
D. 3 cycles
Answer: A
Solution:
Load value available only after MEM → 1-cycle stall needed.
73
Branch prediction can improve pipeline performance by:
A. Reducing control hazards
B. Eliminating RAW hazards
C. Removing structural hazards
D. None
Answer: A
Solution:
Correct prediction avoids flushing → reduces control hazard penalty.
74
Instruction pipeline CPI with 5% stalls = ?
A. 1.05
B. 1
C. 1.1
D. 0.95
Answer: A
Solution:
CPI = ideal 1 + stall fraction = 1 + 0.05 = 1.05.
75
Pipeline with 5 stages executes 50 instructions. Ideal CPI = ?
A. 1
B. 1.2
C. 0.8
D. 2
Answer: A
Solution:
Perfectly pipelined → CPI = 1.
76
Which hazard cannot be resolved by forwarding alone?
A. Load-use hazard
B. ALU RAW hazard
C. Forwarding resolves all hazards
D. None
Answer: A
Solution:
Load-use needs MEM data → stall required even with forwarding.
77
Branch delay slot is:
A. Instruction executed immediately after branch
B. Instruction executed before branch
C. NOP
D. Ignored
Answer: A
Solution:
Delay slot executes regardless of branch outcome.
78
Structural hazard arises due to:
A. Resource contention
B. Data dependency
C. Branch misprediction
D. None
Answer: A
Solution:
Multiple instructions compete for same resource → hazard occurs.
79
Out-of-order execution primarily avoids:
A. WAW and WAR hazards
B. RAW hazards
C. Structural hazards
D. Control hazards
Answer: A
Solution:
By executing independent instructions out-of-order, WAW and WAR can be avoided.
80
Pipeline with branch misprediction penalty = 2 cycles, branch frequency 20%, mispredict rate 30%. Average CPI penalty = ?
A. 0.12
B. 0.1
C. 0.2
D. 0.15
Answer: A
Solution:
CPI penalty = 0.2 × 0.3 × 2 = 0.12 cycles.
81
Which hazard requires flushing instructions?
A. Control hazard
B. RAW
C. WAW
D. WAR
Answer: A
Solution:
Control hazard due to branch misprediction → flush incorrect instructions.
82
Pipeline stage latencies: IF=180 ps, ID=160 ps, EX=200 ps, MEM=180 ps, WB=120 ps, register overhead=20 ps. Clock period = ?
A. 220 ps
B. 200 ps
C. 240 ps
D. 180 ps
Answer: A
Solution:
Max(stage + overhead) = EX 200 + 20 = 220 ps.
83
Number of stall cycles for load-use dependency in 5-stage pipeline = ?
A. 1
B. 0
C. 2
D. 3
Answer: A
Solution:
Load result available after MEM → 1 stall cycle required.
84
Structural hazard occurs in pipeline if:
A. Instructions need same functional unit simultaneously
B. RAW dependency exists
C. Branch mispredicted
D. Pipeline depth increases
Answer: A
Solution:
Resource conflict → structural hazard.
85
WAW hazard avoided by:
A. Register renaming
B. Forwarding
C. Branch prediction
D. Increasing pipeline stages
Answer: A
Solution:
Unique physical registers prevent WAW hazard.
86
A pipeline executes 100 instructions, branch frequency = 10%, misprediction = 25%, penalty = 2 cycles. Total branch penalty cycles = ?
A. 5
B. 10
C. 6
D. 4
Answer: C
Solution:
100 × 0.1 × 0.25 × 2 = 5 → Wait, 1000.1=10 → 100.25=2.5 → 2.5*2=5 cycles → Answer: A. ✅
87
Which hazard is caused by resource conflicts?
A. Structural
B. RAW
C. WAW
D. WAR
Answer: A
Solution:
Structural hazard occurs due to hardware contention.
88
Forwarding path EX→EX resolves:
A. ALU RAW hazards
B. Load-use hazard
C. Control hazards
D. Structural hazards
Answer: A
Solution:
EX→EX feeds ALU output directly → resolves ALU RAW hazard.
89
Pipeline stall due to control hazard arises when:
A. Branch mispredicted
B. RAW hazard exists
C. WAW hazard exists
D. Structural hazard exists
Answer: A
Solution:
Incorrectly fetched instructions after branch → stall required.
90
Pipeline CPI formula:
A. CPI = 1 + branch fraction × misprediction rate × penalty
B. CPI = 1 – penalty
C. CPI = ideal × penalty
D. CPI = 1 only
Answer: A
Solution:
Average CPI = ideal CPI + expected branch penalty.
91
In a 5-stage pipeline, first instruction completes in:
A. 5 cycles
B. 4 cycles
C. 1 cycle
D. 6 cycles
Answer: A
Solution:
Number of stages = 5 → first instruction completes after 5 cycles.
92
WAR hazard avoided by:
A. Register renaming
B. Forwarding
C. Structural duplication
D. Delay slots
Answer: A
Solution:
Renaming ensures later instruction writes different register → avoids WAR.
93
Load-use hazard occurs when:
A. Instruction uses loaded register immediately after load
B. Two ALU instructions in sequence
C. Branch instruction occurs
D. Structural conflict occurs
Answer: A
Solution:
Dependent instruction uses value not yet available → stall needed.
94
Pipeline with 5 stages executes 50 instructions. Total cycles with no stalls = ?
A. 50 + 4 = 54
B. 50
C. 55
D. 49
Answer: A
Solution:
Cycles = pipeline fill (5–1=4) + 50 instructions = 54 cycles.
95
Control hazard can be reduced by:
A. Branch prediction
B. Forwarding
C. Pipeline duplication
D. Register renaming
Answer: A
Solution:
Branch prediction reduces incorrect fetches → fewer stalls.
96
Which hazard requires inserting NOPs?
A. Load-use hazard
B. WAW hazard
C. Structural hazard
D. None
Answer: A
Solution:
1 stall cycle inserted to wait for load → NOP.
97
Pipeline performance degraded mainly by:
A. Hazards
B. Register file size
C. Cache size
D. ALU width
Answer: A
Solution:
Data, control, structural hazards → stalls → CPI increases.
98
Pipeline with branch misprediction frequency f, penalty c. Average CPI = ?
A. 1 + f × c
B. 1 – f × c
C. f × c
D. 1
Answer: A
Solution:
CPI = ideal 1 + average branch penalty.
99
Structural hazard in memory occurs when:
A. Instruction fetch and data access use same port
B. Data dependency exists
C. Branch mispredicted
D. WAW occurs
Answer: A
Solution:
Single-port memory → IF and MEM stages conflict → stall.
100
Forwarding in pipeline is used to:
A. Avoid RAW hazards
B. Avoid WAW hazards
C. Avoid structural hazards
D. Reduce branch penalty
Answer: A
Solution:
Forwarding feeds ALU output to dependent instruction → resolves RAW.
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